int src_w;
int src_h;
bool visible;
+ /*
+ * Display surface base address adjustement for
+ * pageflips. Note that on gen4+ this only adjusts up
+ * to a tile, offsets within a tile are handled in
+ * the hw itself (with the TILEOFF register).
+ */
+ int adjusted_x;
+ int adjusted_y;
} plane;
struct {
else
crtc->dspaddr_offset = linear_offset;
- crtc->adjusted_x = x;
- crtc->adjusted_y = y;
-
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
if (INTEL_GEN(dev_priv) < 4) {
crtc->dspaddr_offset = surf_addr;
- crtc->adjusted_x = src_x;
- crtc->adjusted_y = src_y;
-
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
* gen4+ this only adjusts up to a tile, offsets within a tile are
* handled in the hw itself (with the TILEOFF register). */
u32 dspaddr_offset;
- int adjusted_x;
- int adjusted_y;
struct intel_crtc_state *config;
*/
static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
{
- return crtc->base.y - crtc->adjusted_y;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_fbc *fbc = &dev_priv->fbc;
+
+ return crtc->base.y - fbc->state_cache.plane.adjusted_y;
}
/*
intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
&effective_h);
- effective_w += crtc->adjusted_x;
- effective_h += crtc->adjusted_y;
+ effective_w += fbc->state_cache.plane.adjusted_x;
+ effective_h += fbc->state_cache.plane.adjusted_y;
return effective_w <= max_w && effective_h <= max_h;
}
cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
cache->plane.visible = plane_state->base.visible;
+ cache->plane.adjusted_x = plane_state->main.x;
+ cache->plane.adjusted_y = plane_state->main.y;
if (!cache->plane.visible)
return;