arm64: dts: mediatek: Get rid of mediatek, larb for MM nodes

After adding device_link between the IOMMU consumer and smi,
the mediatek,larb is unnecessary now.

CC: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220421035111.7267-3-allen-kh.cheng@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 848e3f3..10291b2 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -1010,7 +1010,6 @@
                                 <&mmsys CLK_MM_MUTEX_32K>;
                        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
                        iommus = <&iommu M4U_PORT_MDP_RDMA0>;
-                       mediatek,larb = <&larb0>;
                        mediatek,vpu = <&vpu>;
                };
 
@@ -1021,7 +1020,6 @@
                                 <&mmsys CLK_MM_MUTEX_32K>;
                        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
                        iommus = <&iommu M4U_PORT_MDP_RDMA1>;
-                       mediatek,larb = <&larb4>;
                };
 
                mdp_rsz0: rsz@14003000 {
@@ -1051,7 +1049,6 @@
                        clocks = <&mmsys CLK_MM_MDP_WDMA>;
                        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
                        iommus = <&iommu M4U_PORT_MDP_WDMA>;
-                       mediatek,larb = <&larb0>;
                };
 
                mdp_wrot0: wrot@14007000 {
@@ -1060,7 +1057,6 @@
                        clocks = <&mmsys CLK_MM_MDP_WROT0>;
                        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
                        iommus = <&iommu M4U_PORT_MDP_WROT0>;
-                       mediatek,larb = <&larb0>;
                };
 
                mdp_wrot1: wrot@14008000 {
@@ -1069,7 +1065,6 @@
                        clocks = <&mmsys CLK_MM_MDP_WROT1>;
                        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
                        iommus = <&iommu M4U_PORT_MDP_WROT1>;
-                       mediatek,larb = <&larb4>;
                };
 
                ovl0: ovl@1400c000 {
@@ -1079,7 +1074,6 @@
                        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
                        clocks = <&mmsys CLK_MM_DISP_OVL0>;
                        iommus = <&iommu M4U_PORT_DISP_OVL0>;
-                       mediatek,larb = <&larb0>;
                        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
                };
 
@@ -1090,7 +1084,6 @@
                        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
                        clocks = <&mmsys CLK_MM_DISP_OVL1>;
                        iommus = <&iommu M4U_PORT_DISP_OVL1>;
-                       mediatek,larb = <&larb4>;
                        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
                };
 
@@ -1101,7 +1094,6 @@
                        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
                        clocks = <&mmsys CLK_MM_DISP_RDMA0>;
                        iommus = <&iommu M4U_PORT_DISP_RDMA0>;
-                       mediatek,larb = <&larb0>;
                        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
                };
 
@@ -1112,7 +1104,6 @@
                        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
                        clocks = <&mmsys CLK_MM_DISP_RDMA1>;
                        iommus = <&iommu M4U_PORT_DISP_RDMA1>;
-                       mediatek,larb = <&larb4>;
                        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
                };
 
@@ -1123,7 +1114,6 @@
                        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
                        clocks = <&mmsys CLK_MM_DISP_RDMA2>;
                        iommus = <&iommu M4U_PORT_DISP_RDMA2>;
-                       mediatek,larb = <&larb4>;
                        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
                };
 
@@ -1134,7 +1124,6 @@
                        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
                        clocks = <&mmsys CLK_MM_DISP_WDMA0>;
                        iommus = <&iommu M4U_PORT_DISP_WDMA0>;
-                       mediatek,larb = <&larb0>;
                        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
                };
 
@@ -1145,7 +1134,6 @@
                        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
                        clocks = <&mmsys CLK_MM_DISP_WDMA1>;
                        iommus = <&iommu M4U_PORT_DISP_WDMA1>;
-                       mediatek,larb = <&larb4>;
                        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
                };
 
@@ -1399,7 +1387,6 @@
                              <0 0x16027800 0 0x800>,   /* VDEC_HWB */
                              <0 0x16028400 0 0x400>;   /* VDEC_HWG */
                        interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
-                       mediatek,larb = <&larb1>;
                        iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
                                 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
                                 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
@@ -1467,7 +1454,6 @@
                        compatible = "mediatek,mt8173-vcodec-enc";
                        reg = <0 0x18002000 0 0x1000>;  /* VENC_SYS */
                        interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
-                       mediatek,larb = <&larb3>;
                        iommus = <&iommu M4U_PORT_VENC_RCPU>,
                                 <&iommu M4U_PORT_VENC_REC>,
                                 <&iommu M4U_PORT_VENC_BSDMA>,
@@ -1495,7 +1481,6 @@
                        clock-names = "jpgdec-smi",
                                      "jpgdec";
                        power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
-                       mediatek,larb = <&larb3>;
                        iommus = <&iommu M4U_PORT_JPGDEC_WDMA>,
                                 <&iommu M4U_PORT_JPGDEC_BSDMA>;
                };
@@ -1529,7 +1514,6 @@
                                 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
                                 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
                                 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
-                       mediatek,larb = <&larb5>;
                        mediatek,vpu = <&vpu>;
                        clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
                        clock-names = "venc_lt_sel";

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index d1448a0..be97285 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1396,7 +1396,6 @@
                        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
                        clocks = <&mmsys CLK_MM_DISP_OVL0>;
                        iommus = <&iommu M4U_PORT_DISP_OVL0>;
-                       mediatek,larb = <&larb0>;
                        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
                };
 
@@ -1407,7 +1406,6 @@
                        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
                        clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
                        iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
-                       mediatek,larb = <&larb0>;
                        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
                };
 
@@ -1418,7 +1416,6 @@
                        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
                        clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
                        iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>;
-                       mediatek,larb = <&larb0>;
                        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
                };
 
@@ -1429,7 +1426,6 @@
                        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
                        clocks = <&mmsys CLK_MM_DISP_RDMA0>;
                        iommus = <&iommu M4U_PORT_DISP_RDMA0>;
-                       mediatek,larb = <&larb0>;
                        mediatek,rdma-fifo-size = <5120>;
                        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
                };
@@ -1441,7 +1437,6 @@
                        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
                        clocks = <&mmsys CLK_MM_DISP_RDMA1>;
                        iommus = <&iommu M4U_PORT_DISP_RDMA1>;
-                       mediatek,larb = <&larb0>;
                        mediatek,rdma-fifo-size = <2048>;
                        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
                };
@@ -1598,7 +1593,6 @@
                        compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc";
                        reg = <0 0x17030000 0 0x1000>;
                        interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>;
-                       mediatek,larb = <&larb4>;
                        iommus = <&iommu M4U_PORT_JPGENC_RDMA>,
                                 <&iommu M4U_PORT_JPGENC_BSDMA>;
                        power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;