drm/exynos: support exynos5422 mipi-dsi

This patch supports mipi dsi for exynos5422. The dsi register
offsets of the exynos5422 are similar with exynos5433. However,
the values of the registers are quite different from the
exynos5433. For example, the exynos5422 uses sw reset like
previous chips.

Change-Id: I82f19afc66c2893a1bfb9d09ea56e631f67921ae
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>

diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt b/Documentation/devicetree/bindings/video/exynos_dsim.txt
index 9112b10108f6ac0617e02b4fe2681662055c0711..a1dfa75ca4ae8096f15f93be6f397b887325c97e 100644 (file)
--- a/Documentation/devicetree/bindings/video/exynos_dsim.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt
@@ -6,6 +6,7 @@ Required properties:
                "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
                "samsung,exynos4415-mipi-dsi" /* for Exynos4415 SoC */
                "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
+               "samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
                "samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
   - reg: physical base address and length of the registers set for the device
   - interrupts: should contain DSI interrupt

diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index ff963051f3636c4b3297c6a0c45160b8d1c92534..b12d255d2d021f19cbdbace04c04283ce8fce33d 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -414,6 +414,24 @@ static unsigned int reg_values[] = {
        [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
 };
 
+static unsigned int exynos5422_reg_values[] = {
+       [RESET_TYPE] = DSIM_SWRST,
+       [PLL_TIMER] = 500,
+       [STOP_STATE_CNT] = 0xf,
+       [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
+       [PHYCTRL_VREG_LP] = 0,
+       [PHYCTRL_SLEW_UP] = 0,
+       [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08),
+       [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d),
+       [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
+       [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30),
+       [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
+       [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a),
+       [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c),
+       [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11),
+       [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d),
+};
+
 static unsigned int exynos5433_reg_values[] = {
        [RESET_TYPE] = DSIM_FUNCRST,
        [PLL_TIMER] = 22200,
@@ -488,6 +506,17 @@ static struct exynos_dsi_driver_data exynos5433_dsi_driver_data = {
        .reg_values = exynos5433_reg_values,
 };
 
+static struct exynos_dsi_driver_data exynos5422_dsi_driver_data = {
+       .reg_ofs = exynos5433_reg_ofs,
+       .plltmr_reg = 0xa0,
+       .has_clklane_stop = 1,
+       .num_clks = 2,
+       .max_freq = 1500,
+       .wait_for_reset = 1,
+       .num_bits_resol = 12,
+       .reg_values = exynos5422_reg_values,
+};
+
 static struct of_device_id exynos_dsi_of_match[] = {
        { .compatible = "samsung,exynos3250-mipi-dsi",
          .data = &exynos3_dsi_driver_data },
@@ -497,6 +526,8 @@ static struct of_device_id exynos_dsi_of_match[] = {
          .data = &exynos4415_dsi_driver_data },
        { .compatible = "samsung,exynos5410-mipi-dsi",
          .data = &exynos5_dsi_driver_data },
+       { .compatible = "samsung,exynos5422-mipi-dsi",
+         .data = &exynos5422_dsi_driver_data },
        { .compatible = "samsung,exynos5433-mipi-dsi",
          .data = &exynos5433_dsi_driver_data },
        { }