x86: cougarcanyon2: Add missing chipset interrupt information

Add Panther Point chipset interrupt pin/PIRQ information, and
enable the generation of PIRQ routing table and MP table.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts
index 946ba06..c1cda73 100644 (file)
--- a/arch/x86/dts/cougarcanyon2.dts
+++ b/arch/x86/dts/cougarcanyon2.dts
@@ -5,6 +5,8 @@
 
 /dts-v1/;
 
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
 /include/ "keyboard.dtsi"
@@ -99,6 +101,50 @@
                        #address-cells = <1>;
                        #size-cells = <1>;
 
+                       irq-router {
+                               compatible = "intel,irq-router";
+                               intel,pirq-config = "pci";
+                               intel,actl-8bit;
+                               intel,actl-addr = <0x44>;
+                               intel,pirq-link = <0x60 8>;
+                               intel,pirq-regmap = <
+                                       PIRQA 0
+                                       PIRQB 1
+                                       PIRQC 2
+                                       PIRQD 3
+                                       PIRQE 8
+                                       PIRQF 9
+                                       PIRQG 10
+                                       PIRQH 11
+                               >;
+                               intel,pirq-mask = <0xcee0>;
+                               intel,pirq-routing = <
+                                       /* Panther Point PCI devices */
+                                       PCI_BDF(0, 2, 0) INTA PIRQA
+                                       PCI_BDF(0, 20, 0) INTA PIRQA
+                                       PCI_BDF(0, 22, 0) INTA PIRQA
+                                       PCI_BDF(0, 22, 1) INTB PIRQB
+                                       PCI_BDF(0, 22, 2) INTC PIRQC
+                                       PCI_BDF(0, 22, 3) INTD PIRQD
+                                       PCI_BDF(0, 25, 0) INTA PIRQA
+                                       PCI_BDF(0, 26, 0) INTA PIRQA
+                                       PCI_BDF(0, 27, 0) INTB PIRQA
+                                       PCI_BDF(0, 28, 0) INTA PIRQA
+                                       PCI_BDF(0, 28, 1) INTB PIRQB
+                                       PCI_BDF(0, 28, 2) INTC PIRQC
+                                       PCI_BDF(0, 28, 3) INTD PIRQD
+                                       PCI_BDF(0, 28, 4) INTA PIRQA
+                                       PCI_BDF(0, 28, 5) INTB PIRQB
+                                       PCI_BDF(0, 28, 6) INTC PIRQC
+                                       PCI_BDF(0, 28, 7) INTD PIRQD
+                                       PCI_BDF(0, 29, 0) INTA PIRQA
+                                       PCI_BDF(0, 31, 2) INTB PIRQB
+                                       PCI_BDF(0, 31, 3) INTC PIRQC
+                                       PCI_BDF(0, 31, 5) INTB PIRQB
+                                       PCI_BDF(0, 31, 6) INTC PIRQC
+                               >;
+                       };
+
                        spi0: spi {
                                #address-cells = <1>;
                                #size-cells = <0>;

diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
index 98d9aa0..eeee252 100644 (file)
--- a/configs/cougarcanyon2_defconfig
+++ b/configs/cougarcanyon2_defconfig
@@ -6,6 +6,8 @@ CONFIG_TARGET_COUGARCANYON2=y
 # CONFIG_HAVE_INTEL_ME is not set
 # CONFIG_ENABLE_MRC_CACHE is not set
 CONFIG_SMP=y
+CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_GENERATE_MP_TABLE=y
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y