[AArch64][PATCH 2/2] PR target/83009: Relax strict address checking for store

pair lanes

gcc/ChangeLog
2018-07-19  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR target/83009
	* config/aarch64/predicates.md (aarch64_mem_pair_lanes_operand): Make
	address check not strict.

gcc/testsuite/ChangeLog
2018-07-19  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR target/83009
	* gcc/target/aarch64/store_v2vec_lanes.c: Add extra tests.

From-SVN: r262881

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0393db3..2f8d59c 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,11 @@
 2018-07-19  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
+       PR target/83009
+       * config/aarch64/predicates.md (aarch64_mem_pair_lanes_operand): Make
+       address check not strict.
+
+2018-07-19  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
        * config/aarch64/aarch64-simd.md (aarch64_simd_mov<VQ:mode>): Replace
        Umq with Umn.
        (store_pair_lanes<mode>): Likewise.

diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index b5a3ee4..d8f377b 100644 (file)
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -227,7 +227,7 @@
 (define_predicate "aarch64_mem_pair_lanes_operand"
   (and (match_code "mem")
        (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
-                                                 true,
+                                                 false,
                                                  ADDR_QUERY_LDP_STP_N)")))
 
 (define_predicate "aarch64_prefetch_operand"

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 8ffc1f3..50a8cdf 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2018-07-19  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+       PR target/83009
+       * gcc/target/aarch64/store_v2vec_lanes.c: Add extra tests.
+
 2018-07-19  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR target/86560

diff --git a/gcc/testsuite/gcc.target/aarch64/store_v2vec_lanes.c b/gcc/testsuite/gcc.target/aarch64/store_v2vec_lanes.c
index 990aea3..3296d04 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/store_v2vec_lanes.c
+++ b/gcc/testsuite/gcc.target/aarch64/store_v2vec_lanes.c
@@ -22,10 +22,32 @@ construct_lane_2 (long long *y, v2di *z)
   z[2] = x;
 }
 
+void
+construct_lane_3 (double **py, v2df **pz)
+{
+  double *y = *py;
+  v2df *z = *pz;
+  double y0 = y[0] + 1;
+  double y1 = y[1] + 2;
+  v2df x = {y0, y1};
+  z[2] = x;
+}
+
+void
+construct_lane_4 (long long **py, v2di **pz)
+{
+  long long *y = *py;
+  v2di *z = *pz;
+  long long y0 = y[0] + 1;
+  long long y1 = y[1] + 2;
+  v2di x = {y0, y1};
+  z[2] = x;
+}
+
 /* We can use the load_pair_lanes<mode> pattern to vec_concat two DI/DF
    values from consecutive memory into a 2-element vector by using
    a Q-reg LDR.  */
 
-/* { dg-final { scan-assembler-times "stp\td\[0-9\]+, d\[0-9\]+" 1 { xfail ilp32 } } } */
-/* { dg-final { scan-assembler-times "stp\tx\[0-9\]+, x\[0-9\]+" 1 { xfail ilp32 } } } */
-/* { dg-final { scan-assembler-not "ins\t" { xfail ilp32 } } } */
+/* { dg-final { scan-assembler-times "stp\td\[0-9\]+, d\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler-times "stp\tx\[0-9\]+, x\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler-not "ins\t" } } */