def int_aarch64_sme_set_tpidr2
: DefaultAttrsIntrinsic<[], [llvm_i64_ty],
[IntrNoMem, IntrHasSideEffects]>;
+
+ def int_aarch64_sme_za_enable
+ : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>;
+ def int_aarch64_sme_za_disable
+ : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>;
+
// Clamp
//
}
}
+ if (Subtarget->hasSME())
+ setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
+
if (Subtarget->hasSVE()) {
for (auto VT : {MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64}) {
setOperationAction(ISD::BITREVERSE, VT, Custom);
SDValue PStateSM = getPStateSM(DAG, Chain, Attrs, DL, Op.getValueType());
return DAG.getMergeValues({PStateSM, Chain}, DL);
}
+ case Intrinsic::aarch64_sme_za_enable:
+ return DAG.getNode(
+ AArch64ISD::SMSTART, DL, MVT::Other,
+ Op->getOperand(0), // Chain
+ DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32),
+ DAG.getConstant(0, DL, MVT::i64), DAG.getConstant(1, DL, MVT::i64));
+ case Intrinsic::aarch64_sme_za_disable:
+ return DAG.getNode(
+ AArch64ISD::SMSTOP, DL, MVT::Other,
+ Op->getOperand(0), // Chain
+ DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32),
+ DAG.getConstant(0, DL, MVT::i64), DAG.getConstant(1, DL, MVT::i64));
}
}
return LowerToPredicatedOp(Op, DAG, AArch64ISD::MULHS_PRED);
case ISD::MULHU:
return LowerToPredicatedOp(Op, DAG, AArch64ISD::MULHU_PRED);
+ case ISD::INTRINSIC_VOID:
case ISD::INTRINSIC_W_CHAIN:
return LowerINTRINSIC_W_CHAIN(Op, DAG);
case ISD::INTRINSIC_WO_CHAIN:
--- /dev/null
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 -mattr=+sme -verify-machineinstrs < %s | FileCheck %s
+
+define void @toggle_pstate_za() {
+; CHECK-LABEL: toggle_pstate_za:
+; CHECK: // %bb.0:
+; CHECK-NEXT: smstart za
+; CHECK-NEXT: smstop za
+; CHECK-NEXT: ret
+ call void @llvm.aarch64.sme.za.enable()
+ call void @llvm.aarch64.sme.za.disable()
+ ret void
+}
+
+declare void @llvm.aarch64.sme.za.enable()
+declare void @llvm.aarch64.sme.za.disable()