if (!NumVariadicOps)
return;
- // FIXME: if an instruction opcode is flagged 'mayStore', and it has no
- // "unmodeledSideEffects', then this logic optimistically assumes that any
- // extra register operands in the variadic sequence is not a register
- // definition.
- //
- // Otherwise, we conservatively assume that any register operand from the
- // variadic sequence is both a register read and a register write.
- bool AssumeUsesOnly = MCDesc.mayStore() && !MCDesc.mayLoad() &&
- !MCDesc.hasUnmodeledSideEffects();
+ bool AssumeUsesOnly = !MCDesc.variadicOpsAreDefs();
CurrentDef = NumExplicitDefs + NumImplicitDefs + MCDesc.hasOptionalDef();
for (unsigned I = 0, OpIndex = MCDesc.getNumOperands();
I < NumVariadicOps && !AssumeUsesOnly; ++I, ++OpIndex) {
CurrentUse += NumImplicitUses;
- // FIXME: If an instruction opcode is marked as 'mayLoad', and it has no
- // "unmodeledSideEffects", then this logic optimistically assumes that any
- // extra register operand in the variadic sequence is not a register
- // definition.
- bool AssumeDefsOnly = !MCDesc.mayStore() && MCDesc.mayLoad() &&
- !MCDesc.hasUnmodeledSideEffects();
+ bool AssumeDefsOnly = MCDesc.variadicOpsAreDefs();
for (unsigned I = 0, OpIndex = MCDesc.getNumOperands();
I < NumVariadicOps && !AssumeDefsOnly; ++I, ++OpIndex) {
const MCOperand &Op = MCI.getOperand(OpIndex);
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 10 5.5 0.1 0.0 pop {r3, r4, r5, r6, r7, pc}
+# CHECK-NEXT: 0. 10 5.5 2.7 0.0 pop {r3, r4, r5, r6, r7, pc}
# CHECK-NEXT: 1. 10 3.6 0.0 3.9 nop
-# CHECK-NEXT: 10 4.6 0.1 2.0 <total>
+# CHECK-NEXT: 10 4.6 1.4 2.0 <total>