radeon: fix bug with wrong stride being used for rectangluar textures.
authorDave Airlie <airlied@redhat.com>
Thu, 10 Nov 2011 13:46:25 +0000 (13:46 +0000)
committerDave Airlie <airlied@redhat.com>
Fri, 11 Nov 2011 15:04:52 +0000 (15:04 +0000)
This broke the meta bitmap code when it was enabled.

Signed-off-by: Dave Airlie <airlied@redhat.com>
src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
src/mesa/drivers/dri/radeon/radeon_pixel_read.c
src/mesa/drivers/dri/radeon/radeon_texture.c

index 7975354..05daf1c 100644 (file)
@@ -96,14 +96,14 @@ unsigned get_texture_image_size(
        return rowStride * height * depth;
 }
 
-unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling)
+unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, GLuint target)
 {
        if (_mesa_is_format_compressed(format)) {
                return get_aligned_compressed_row_stride(format, width, rmesa->texture_compressed_row_align);
        } else {
                unsigned row_align;
 
-               if (!_mesa_is_pow_two(width)) {
+               if (!_mesa_is_pow_two(width) || target == GL_TEXTURE_RECTANGLE) {
                        row_align = rmesa->texture_rect_row_align - 1;
                } else if (tiling) {
                        unsigned tileWidth, tileHeight;
@@ -132,7 +132,7 @@ static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree
 
        height = _mesa_next_pow_two_32(lvl->height);
 
-       lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width, mt->tilebits);
+       lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width, mt->tilebits, mt->target);
        lvl->size = get_texture_image_size(mt->mesaFormat, lvl->rowstride, height, lvl->depth, mt->tilebits);
 
        assert(lvl->size > 0);
index a68a976..c0c52f0 100644 (file)
@@ -90,7 +90,7 @@ GLuint radeon_miptree_image_offset(radeon_mipmap_tree *mt,
                                   GLuint face, GLuint level);
 uint32_t get_base_teximage_offset(radeonTexObj *texObj);
 
-unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling);
+unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, unsigned target);
 
 unsigned get_texture_image_size(
                gl_format format,
index 62e0471..b819ac4 100644 (file)
@@ -128,7 +128,7 @@ do_blit_readpixels(struct gl_context * ctx,
     }
     assert(x >= 0 && y >= 0);
 
-    aligned_rowstride = get_texture_image_row_stride(radeon, dst_format, dst_rowstride, 0);
+    aligned_rowstride = get_texture_image_row_stride(radeon, dst_format, dst_rowstride, 0, GL_TEXTURE_2D);
     dst_rowstride *= _mesa_get_format_bytes(dst_format);
     if (_mesa_is_bufferobj(pack->BufferObj) && aligned_rowstride != dst_rowstride)
         return GL_FALSE;
index 6e81493..85ee113 100644 (file)
@@ -299,7 +299,7 @@ radeon_map_texture_image(struct gl_context *ctx,
        if (image->bo) {
                /* TFP case */
                radeon_bo_map(image->bo, write);
-               *stride = get_texture_image_row_stride(rmesa, texImage->TexFormat, width, 0);
+               *stride = get_texture_image_row_stride(rmesa, texImage->TexFormat, width, 0, texImage->TexObject->Target);
                *map = bo->ptr;
        } else if (likely(mt)) {
                radeon_bo_map(mt->bo, write);