h8300.md (a peephole2): Extend to support loads in QImode and HImode.

	* config/h8300/h8300.md (a peephole2): Extend to support loads
	in QImode and HImode.

From-SVN: r64836

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2dca24b..7c6d4ee 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2003-03-24  Kazu Hirata  <kazu@cs.umass.edu>
+
+       * config/h8300/h8300.md (a peephole2): Extend to support loads
+       in QImode and HImode.
+
 2003-03-24  Stephane Carrez  <stcarrez@nerim.fr>
 
        * config/m68hc11/t-m68hc11-gas (LIB1ASMFUNCS): Add _call_far and

diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index 43bca10..b9a6094 100644 (file)
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -3775,6 +3775,17 @@
                  ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
                  : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));")
 
+;; The next three peephole2's will try to transform
+;;
+;;   mov.b A,r0l    (or mov.l A,er0)
+;;   and.l #CST,er0
+;;
+;; into
+;;
+;;   sub.l er0
+;;   mov.b A,r0l
+;;   and.b #CST,r0l (if CST is not 255)
+
 (define_peephole2
   [(set (match_operand:QI 0 "register_operand" "")
        (match_operand:QI 1 "general_operand" ""))
@@ -3807,24 +3818,31 @@
    operands[3] = gen_lowpart (QImode, operands[1]);")
 
 (define_peephole2
-  [(set (match_operand:SI 0 "register_operand" "")
-       (match_operand:SI 1 "general_operand" ""))
-   (set (match_dup 0)
-       (and:SI (match_dup 0)
-               (match_operand:SI 2 "const_int_qi_operand" "")))]
+  [(set (match_operand 0 "register_operand" "")
+       (match_operand 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+       (and:SI (match_dup 2)
+               (match_operand:SI 3 "const_int_qi_operand" "")))]
   "(TARGET_H8300H || TARGET_H8300S)
-   && !reg_overlap_mentioned_p (operands[0], operands[1])
-   && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
-  [(set (match_dup 0)
+   && (GET_MODE (operands[0]) == QImode
+       || GET_MODE (operands[0]) == HImode
+       || GET_MODE (operands[0]) == SImode)
+   && GET_MODE (operands[0]) == GET_MODE (operands[1])
+   && REGNO (operands[0]) == REGNO (operands[2])
+   && !reg_overlap_mentioned_p (operands[2], operands[1])
+   && !(GET_MODE (operands[1]) != QImode
+       && GET_CODE (operands[1]) == MEM
+       && MEM_VOLATILE_P (operands[1]))"
+  [(set (match_dup 2)
        (const_int 0))
-   (set (strict_low_part (match_dup 3))
-       (match_dup 4))
-   (set (match_dup 0)
-       (and:SI (match_dup 0)
-               (match_dup 5)))]
-  "operands[3] = gen_lowpart (QImode, operands[0]);
-   operands[4] = gen_lowpart (QImode, operands[1]);
-   operands[5] = GEN_INT (~0xff | INTVAL (operands[2]));")
+   (set (strict_low_part (match_dup 4))
+       (match_dup 5))
+   (set (match_dup 2)
+       (and:SI (match_dup 2)
+               (match_dup 6)))]
+  "operands[4] = gen_lowpart (QImode, operands[0]);
+   operands[5] = gen_lowpart (QImode, operands[1]);
+   operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));")
 
 (define_peephole2
   [(set (match_operand:SI 0 "register_operand" "")