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pwm: img: Test clock rate to avoid division by 0
author
Wolfram Sang
<wsa+renesas@sang-engineering.com>
Wed, 2 Mar 2016 22:33:34 +0000
(23:33 +0100)
committer
Thierry Reding
<thierry.reding@gmail.com>
Wed, 23 Mar 2016 16:11:02 +0000
(17:11 +0100)
The clk API may return 0 on clk_get_rate(), so we should check the
result before using it as a divisor.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
drivers/pwm/pwm-img.c
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diff --git
a/drivers/pwm/pwm-img.c
b/drivers/pwm/pwm-img.c
index
8a029f9
..
2fb30de
100644
(file)
--- a/
drivers/pwm/pwm-img.c
+++ b/
drivers/pwm/pwm-img.c
@@
-237,6
+237,11
@@
static int img_pwm_probe(struct platform_device *pdev)
}
clk_rate = clk_get_rate(pwm->pwm_clk);
+ if (!clk_rate) {
+ dev_err(&pdev->dev, "pwm clock has no frequency\n");
+ ret = -EINVAL;
+ goto disable_pwmclk;
+ }
/* The maximum input clock divider is 512 */
val = (u64)NSEC_PER_SEC * 512 * pwm->data->max_timebase;