/dts-v1/;
#include "mesong12a.dtsi"
-
+#include "partition_mbox_normal.dtsi"
/ {
model = "Amlogic";
compatible = "amlogic, g12a";
};
};
+
vdac {
compatible = "amlogic, vdac";
dev_name = "vdac";
status = "okay";
};
+
+ sd_emmc_c: emmc@ffe07000 {
+ status = "okay";
+ compatible = "amlogic, meson-mmc-g12a";
+ reg = <0x0 0xffe07000 0x0 0x2000>;
+ interrupts = <0 191 1>;
+ pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins";
+ pinctrl-0 = <&emmc_clk_cmd_pins>;
+ pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>;
+ clocks = <&clkc CLKID_SD_EMMC_C>,
+ <&clkc CLKID_SD_EMMC_C_P0_COMP>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_FCLK_DIV5>,
+ <&xtal>;
+ clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal";
+
+ bus-width = <8>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ /* mmc-ddr-1_8v; */
+ /* mmc-hs200-1_8v; */
+
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ emmc {
+ pinname = "emmc";
+ ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */
+ caps = "MMC_CAP_8_BIT_DATA",
+ "MMC_CAP_MMC_HIGHSPEED",
+ "MMC_CAP_SD_HIGHSPEED",
+ "MMC_CAP_NONREMOVABLE",
+ /* "MMC_CAP_1_8V_DDR", */
+ "MMC_CAP_HW_RESET",
+ "MMC_CAP_ERASE",
+ "MMC_CAP_CMD23";
+ /* caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";*/
+ f_min = <400000>;
+ f_max = <200000000>;
+ tx_delay = <0>;
+ max_req_size = <0x20000>; /**128KB*/
+ gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>;
+ hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>;
+ card_type = <1>;
+ /* 1:mmc card(include eMMC),
+ * 2:sd card(include tSD)
+ */
+ };
+ };
+
sd_emmc_b:sd@ffe05000 {
status = "okay";
compatible = "amlogic, meson-mmc-g12a";
};
&pinctrl_periphs {
+ /* sdemmc portC */
+ emmc_clk_cmd_pins:emmc_clk_cmd_pins {
+ mux {
+ groups = "emmc_clk",
+ "emmc_cmd";
+ function = "emmc";
+ input-enable;
+ bias-pull-up;
+ };
+ };
+
+ emmc_conf_pull_up:emmc_conf_pull_up {
+ mux {
+ groups = "emmc_nand_d7",
+ "emmc_nand_d6",
+ "emmc_nand_d5",
+ "emmc_nand_d4",
+ "emmc_nand_d3",
+ "emmc_nand_d2",
+ "emmc_nand_d1",
+ "emmc_nand_d0",
+ "emmc_clk",
+ "emmc_cmd";
+ function = "emmc";
+ input-enable;
+ bias-pull-up;
+ };
+ };
+
+ emmc_conf_pull_done:emmc_conf_pull_done {
+ mux {
+ groups = "emmc_nand_ds";
+ function = "emmc";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ sd_clk_cmd_pins:sd_clk_cmd_pins {
+ mux {
+ groups = "sdcard_cmd_c",
+ "sdcard_clk_c";
+ function = "sdcard";
+ input-enable;
+ bias-pull-up;
+ };
+ };
/* sdemmc portB */
sd_clk_cmd_pins:sd_clk_cmd_pins {
mux {
clkc->core_phase = 2;
pr_info("%s: try set sd/emmc to DDR mode\n",
mmc_hostname(host->mmc));
- } else if (timing == MMC_TIMING_MMC_HS)
+ } else if ((timing == MMC_TIMING_MMC_HS)
+ && (host->data->chip_type < MMC_CHIP_G12A))
clkc->core_phase = 3;
else if ((timing == MMC_TIMING_MMC_HS200)
|| ((timing == MMC_TIMING_SD_HS)