platform/x86/amd: pmc: Get STB DRAM size from PMFW
authorShyam Sundar S K <Shyam-sundar.S-k@amd.com>
Thu, 25 May 2023 14:19:27 +0000 (19:49 +0530)
committerHans de Goede <hdegoede@redhat.com>
Tue, 30 May 2023 09:08:10 +0000 (11:08 +0200)
Recent PMFW's have support for querying the STB DRAM size. Add this
support to the driver.

Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Co-developed-by: Sanket Goswami <Sanket.Goswami@amd.com>
Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Link: https://lore.kernel.org/r/20230525141929.866385-3-Shyam-sundar.S-k@amd.com
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
drivers/platform/x86/amd/pmc.c

index f28c295..e2439fd 100644 (file)
@@ -115,6 +115,7 @@ enum s2d_arg {
        S2D_PHYS_ADDR_LOW,
        S2D_PHYS_ADDR_HIGH,
        S2D_NUM_SAMPLES,
+       S2D_DRAM_SIZE,
 };
 
 struct amd_pmc_bit_map {
@@ -147,6 +148,7 @@ struct amd_pmc_dev {
        u32 base_addr;
        u32 cpu_id;
        u32 active_ips;
+       u32 dram_size;
 /* SMU version information */
        u8 smu_program;
        u8 major;
@@ -890,11 +892,39 @@ static const struct pci_device_id pmc_pci_ids[] = {
        { }
 };
 
+static int amd_pmc_get_dram_size(struct amd_pmc_dev *dev)
+{
+       int ret;
+
+       switch (dev->cpu_id) {
+       case AMD_CPU_ID_YC:
+               if (!(dev->major > 90 || (dev->major == 90 && dev->minor > 39))) {
+                       ret = -EINVAL;
+                       goto err_dram_size;
+               }
+               break;
+       default:
+               ret = -EINVAL;
+               goto err_dram_size;
+       }
+
+       ret = amd_pmc_send_cmd(dev, S2D_DRAM_SIZE, &dev->dram_size, STB_SPILL_TO_DRAM, true);
+       if (ret || !dev->dram_size)
+               goto err_dram_size;
+
+       return 0;
+
+err_dram_size:
+       dev_err(dev->dev, "DRAM size command not supported for this platform\n");
+       return ret;
+}
+
 static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
 {
        u32 phys_addr_low, phys_addr_hi;
        u64 stb_phys_addr;
        u32 size = 0;
+       int ret;
 
        /* Spill to DRAM feature uses separate SMU message port */
        dev->msg_port = 1;
@@ -903,6 +933,11 @@ static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
        if (size != S2D_TELEMETRY_BYTES_MAX)
                return -EIO;
 
+       /* Get DRAM size */
+       ret = amd_pmc_get_dram_size(dev);
+       if (ret)
+               dev->dram_size = S2D_TELEMETRY_DRAMBYTES_MAX;
+
        /* Get STB DRAM address */
        amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, STB_SPILL_TO_DRAM, true);
        amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, STB_SPILL_TO_DRAM, true);
@@ -912,7 +947,7 @@ static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
        /* Clear msg_port for other SMU operation */
        dev->msg_port = 0;
 
-       dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, S2D_TELEMETRY_DRAMBYTES_MAX);
+       dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, dev->dram_size);
        if (!dev->stb_virt_addr)
                return -ENOMEM;