[PPC][AIX] Add vector callee saved registers for AIX extended vector ABI

This patch is the initial patch for support of the AIX extended vector ABI.  The extended ABI treats vector registers V20-V31 as non-volatile and we add them as callee saved registers in this patch.

Reviewed By: sfertile

Differential Revision: https://reviews.llvm.org/D88676

diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h
index 3b41b97..14ec0a3 100644 (file)
--- a/llvm/include/llvm/Target/TargetMachine.h
+++ b/llvm/include/llvm/Target/TargetMachine.h
@@ -243,6 +243,10 @@ public:
     Options.SupportsDebugEntryValues = Enable;
   }
 
+  bool getAIXExtendedAltivecABI() const {
+    return Options.EnableAIXExtendedAltivecABI;
+  }
+
   bool getUniqueSectionNames() const { return Options.UniqueSectionNames; }
 
   /// Return true if unique basic block section names must be generated.

diff --git a/llvm/lib/Target/PowerPC/PPCCallingConv.td b/llvm/lib/Target/PowerPC/PPCCallingConv.td
index 64de735..cc34867 100644 (file)
--- a/llvm/lib/Target/PowerPC/PPCCallingConv.td
+++ b/llvm/lib/Target/PowerPC/PPCCallingConv.td
@@ -291,6 +291,8 @@ def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
                                      F27, F28, F29, F30, F31, CR2, CR3, CR4
                                 )>;
 
+def CSR_AIX32_Altivec : CalleeSavedRegs<(add CSR_AIX32, CSR_Altivec)>;
+
 // Common CalleeSavedRegs for SVR4 and AIX.
 def CSR_PPC64   : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
                                         X21, X22, X23, X24, X25, X26, X27, X28,

diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
index 6f1fe4e..95bcace 100644 (file)
--- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -218,19 +218,14 @@ const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(
       CALLEE_SAVED_VRS
   };
 
-  static const SpillSlot AIXOffsets32[] = {
-      CALLEE_SAVED_FPRS,
-      CALLEE_SAVED_GPRS32,
-      // Add AIX's extra CSR.
-      {PPC::R13, -76},
-      // TODO: Update when we add vector support for AIX.
-  };
+  static const SpillSlot AIXOffsets32[] = {CALLEE_SAVED_FPRS,
+                                           CALLEE_SAVED_GPRS32,
+                                           // Add AIX's extra CSR.
+                                           {PPC::R13, -76},
+                                           CALLEE_SAVED_VRS};
 
   static const SpillSlot AIXOffsets64[] = {
-      CALLEE_SAVED_FPRS,
-      CALLEE_SAVED_GPRS64,
-      // TODO: Update when we add vector support for AIX.
-  };
+      CALLEE_SAVED_FPRS, CALLEE_SAVED_GPRS64, CALLEE_SAVED_VRS};
 
   if (Subtarget.is64BitELFABI()) {
     NumEntries = array_lengthof(ELFOffsets64);

diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 7dd495c..9ff6bdd 100644 (file)
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -156,6 +156,10 @@ PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
 const MCPhysReg*
 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
+  if (Subtarget.isAIXABI() &&
+      (Subtarget.hasAltivec() && !TM.getAIXExtendedAltivecABI()))
+    report_fatal_error("the default AIX Altivec ABI is not yet "
+                       "supported.");
   if (MF->getFunction().getCallingConv() == CallingConv::AnyReg) {
     if (!TM.isPPC64() && Subtarget.isAIXABI())
       report_fatal_error("AnyReg unimplemented on 32-bit AIX.");
@@ -202,8 +206,11 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
     return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
   }
   // 32-bit targets.
-  if (Subtarget.isAIXABI())
+  if (Subtarget.isAIXABI()) {
+    if (Subtarget.hasAltivec())
+      return CSR_AIX32_Altivec_SaveList;
     return CSR_AIX32_SaveList;
+  }
   if (Subtarget.hasAltivec())
     return CSR_SVR432_Altivec_SaveList;
   else if (Subtarget.hasSPE())

diff --git a/llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll b/llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll
index 2809aab..5ed48e9 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < \
 ; RUN: %s | FileCheck %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < \
 ; RUN: %s | FileCheck %s
 
 @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @foo, i8* null }]

diff --git a/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll b/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
new file mode 100644 (file)
index 0000000..744ec2f
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
@@ -0,0 +1,308 @@
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -vec-extabi -verify-machineinstrs -mcpu=pwr7 \
+; RUN:     -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN:   FileCheck --check-prefix=MIR32 %s
+
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -vec-extabi -verify-machineinstrs \
+; RUN:     -mcpu=pwr7 -mattr=+altivec < %s | \
+; RUN:   FileCheck --check-prefix=ASM32 %s
+
+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -vec-extabi -verify-machineinstrs \
+; RUN:     -mcpu=pwr7 -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN:   FileCheck --check-prefix=MIR64 %s
+
+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -vec-extabi -verify-machineinstrs \
+; RUN:     -mcpu=pwr7 -mattr=+altivec < %s | \
+; RUN:   FileCheck --check-prefix=ASM64 %s
+
+
+define dso_local void @vec_regs() {
+entry:
+  call void asm sideeffect "", "~{v13},~{v20},~{v26},~{v31}"()
+  ret void
+}
+
+; MIR32:         name:            vec_regs
+
+; MIR32-LABEL:   fixedStack:
+; MIR32-NEXT:    - { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 1, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 2, type: spill-slot, offset: -192, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    stack:
+
+; MIR32:         liveins: $v20, $v26, $v31
+
+; MIR32-DAG:     STXVD2X killed $v20, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.2)
+; MIR32-DAG:     STXVD2X killed $v26, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.1)
+; MIR32-DAG:     STXVD2X killed $v31, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.0)
+
+; MIR32:         INLINEASM
+
+; MIR32-DAG:     $v20 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.2)
+; MIR32-DAG:     $v26 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.1)
+; MIR32-DAG:     $v31 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.0)
+; MIR32:         BLR implicit $lr, implicit $rm
+
+; MIR64:         name:            vec_regs
+
+; MIR64-LABEL:   fixedStack:
+; MIR64-NEXT:    - { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 1, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 2, type: spill-slot, offset: -192, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    stack:
+
+; MIR64:         liveins: $v20, $v26, $v31
+
+; MIR64-DAG:     STXVD2X killed $v20, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.2)
+; MIR64-DAG:     STXVD2X killed $v26, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.1)
+; MIR64-DAG:     STXVD2X killed $v31, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.0)
+
+; MIR64:         INLINEASM
+
+; MIR64-DAG:     $v20 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.2)
+; MIR64-DAG:     $v26 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.1)
+; MIR64-DAG:     $v31 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.0)
+; MIR64:         BLR8 implicit $lr8, implicit $rm
+
+
+; ASM32-LABEL:   .vec_regs:
+
+; ASM32:         li {{[0-9]+}}, -192
+; ASM32-DAG:     stxvd2x 52, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM32-DAG:     li {{[0-9]+}}, -96
+; ASM32-DAG:     stxvd2x 58, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM32-DAG:     li {{[0-9]+}}, -16
+; ASM32-DAG:     stxvd2x 63, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM32:         #APP
+; ASM32-DAG:     #NO_APP
+; ASM32-DAG:     lxvd2x 63, 1, {{[0-9]+}}       # 16-byte Folded Reload
+; ASM32-DAG:     li {{[0-9]+}}, -96
+; ASM32-DAG:     lxvd2x 58, 1, {{[0-9]+}}       # 16-byte Folded Reload
+; ASM32-DAG:     li {{[0-9]+}}, -192
+; ASM32-DAG:     lxvd2x 52, 1, {{[0-9]+}}       # 16-byte Folded Reload
+; ASM32:         blr
+
+; ASM64-LABEL:   .vec_regs:
+
+; ASM64-DAG:     li {{[0-9]+}}, -192
+; ASM64-DAG:     stxvd2x 52, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM64-DAG:     li {{[0-9]+}}, -96
+; ASM64-DAG:     stxvd2x 58, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM64-DAG:     li {{[0-9]+}}, -16
+; ASM64-DAG:     stxvd2x {{[0-9]+}}, 1, {{[0-9]+}}      # 16-byte Folded Spill
+; ASM64-DAG:     #APP
+; ASM64-DAG:     #NO_APP
+; ASM64-DAG:     lxvd2x {{[0-9]+}}, 1, {{[0-9]+}}       # 16-byte Folded Reload
+; ASM64-DAG:     li {{[0-9]+}}, -96
+; ASM64-DAG:     lxvd2x 58, 1, {{[0-9]+}}                # 16-byte Folded Reload
+; ASM64-DAG:     li {{[0-9]+}}, -192
+; ASM64-DAG:     lxvd2x 52, 1, {{[0-9]+}}                # 16-byte Folded Reload
+; ASM64-DAG:     blr
+
+define dso_local void @fprs_gprs_vecregs() {
+  call void asm sideeffect "", "~{r14},~{r25},~{r31},~{f14},~{f21},~{f31},~{v20},~{v26},~{v31}"()
+  ret void
+}
+
+; MIR32:         name:            fprs_gprs_vecregs
+
+; MIR32-LABEL:   fixedStack:
+; MIR32-NEXT:    - { id: 0, type: spill-slot, offset: -240, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 1, type: spill-slot, offset: -320, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 2, type: spill-slot, offset: -416, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 3, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 4, type: spill-slot, offset: -88, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 5, type: spill-slot, offset: -144, size: 8, alignment: 16, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$f14', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 6, type: spill-slot, offset: -148, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$r31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 7, type: spill-slot, offset: -172, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$r25', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 8, type: spill-slot, offset: -216, size: 4, alignment: 8, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$r14', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    stack:
+
+; MIR32:         liveins: $r14, $r25, $r31, $f14, $f21, $f31, $v20, $v26, $v31
+
+; MIR32-DAG:     STW killed $r14, 232, $r1 :: (store 4 into %fixed-stack.8, align 8)
+; MIR32-DAG:     STW killed $r25, 276, $r1 :: (store 4 into %fixed-stack.7)
+; MIR32-DAG:     STW killed $r31, 300, $r1 :: (store 4 into %fixed-stack.6)
+; MIR32-DAG:     STFD killed $f14, 304, $r1 :: (store 8 into %fixed-stack.5, align 16)
+; MIR32-DAG:     STFD killed $f21, 360, $r1 :: (store 8 into %fixed-stack.4)
+; MIR32-DAG:     STFD killed $f31, 440, $r1 :: (store 8 into %fixed-stack.3)
+; MIR32-DAG:     $r{{[0-9]+}} = LI 32
+; MIR32-DAG:     STXVD2X killed $v20, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.2)
+; MIR32-DAG:     $r{{[0-9]+}} = LI 128
+; MIR32-DAG:     STXVD2X killed $v26, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.1)
+; MIR32-DAG:     $r{{[0-9]+}} = LI 208
+; MIR32-DAG:     STXVD2X killed $v31, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.0)
+; MIR32-DAG:     $r1 = STWU $r1, -448, $r1
+
+; MIR32:         INLINEASM
+
+; MIR32-DAG:     $r14 = LWZ 232, $r1 :: (load 4 from %fixed-stack.8, align 8)
+; MIR32-DAG:     $r25 = LWZ 276, $r1 :: (load 4 from %fixed-stack.7)
+; MIR32-DAG:     $r31 = LWZ 300, $r1 :: (load 4 from %fixed-stack.6)
+; MIR32-DAG:     $f14 = LFD 304, $r1 :: (load 8 from %fixed-stack.5, align 16)
+; MIR32-DAG:     $f21 = LFD 360, $r1 :: (load 8 from %fixed-stack.4)
+; MIR32-DAG:     $f31 = LFD 440, $r1 :: (load 8 from %fixed-stack.3)
+; MIR32-DAG:     $v20 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.2)
+; MIR32-DAG:     $r{{[0-9]+}} = LI 32
+; MIR32-DAG:     $v26 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.1)
+; MIR32-DAG:     $r{{[0-9]+}} = LI 128
+; MIR32-DAG:     $v31 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.0)
+; MIR32-DAG:     $r{{[0-9]+}} = LI 208
+; MIR32-DAG:     $r1 = ADDI $r1, 448
+; MIR32-DAG:     BLR implicit $lr, implicit $rm
+
+; MIR64:         name:            fprs_gprs_vecregs
+
+; MIR64-LABEL:   fixedStack:
+; MIR64-NEXT:    - { id: 0, type: spill-slot, offset: -304, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 1, type: spill-slot, offset: -384, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 2, type: spill-slot, offset: -480, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 3, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 4, type: spill-slot, offset: -88, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 5, type: spill-slot, offset: -144, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$f14', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 6, type: spill-slot, offset: -152, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$x31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 7, type: spill-slot, offset: -200, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$x25', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 8, type: spill-slot, offset: -288, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$x14', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    stack:
+
+; MIR64:         liveins: $x14, $x25, $x31, $f14, $f21, $f31, $v20, $v26, $v31
+
+; MIR64-DAG:     $x1 = STDU $x1, -544, $x1
+; MIR64-DAG:     STD killed $x14, 256, $x1 :: (store 8 into %fixed-stack.8, align 16)
+; MIR64-DAG:     STD killed $x25, 344, $x1 :: (store 8 into %fixed-stack.7)
+; MIR64-DAG:     STD killed $x31, 392, $x1 :: (store 8 into %fixed-stack.6)
+; MIR64-DAG:     STFD killed $f14, 400, $x1 :: (store 8 into %fixed-stack.5, align 16)
+; MIR64-DAG:     STFD killed $f21, 456, $x1 :: (store 8 into %fixed-stack.4)
+; MIR64-DAG:     STFD killed $f31, 536, $x1 :: (store 8 into %fixed-stack.3)
+; MIR64-DAG:     $x{{[0-9]+}} = LI8 64
+; MIR64-DAG:     STXVD2X killed $v20, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.2)
+; MIR64-DAG:     $x{{[0-9]+}} = LI8 160
+; MIR64-DAG:     STXVD2X killed $v26, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.1)
+; MIR64-DAG:     $x{{[0-9]+}} = LI8 240
+; MIR64-DAG:     STXVD2X killed $v31, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.0)
+
+; MIR64:         INLINEASM
+
+; MIR64-DAG:     $x14 = LD 256, $x1 :: (load 8 from %fixed-stack.8, align 16)
+; MIR64-DAG:     $x25 = LD 344, $x1 :: (load 8 from %fixed-stack.7)
+; MIR64-DAG:     $x31 = LD 392, $x1 :: (load 8 from %fixed-stack.6)
+; MIR64-DAG:     $f14 = LFD 400, $x1 :: (load 8 from %fixed-stack.5, align 16)
+; MIR64-DAG:     $f21 = LFD 456, $x1 :: (load 8 from %fixed-stack.4)
+; MIR64-DAG:     $f31 = LFD 536, $x1 :: (load 8 from %fixed-stack.3)
+; MIR64-DAG:     $v20 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.2)
+; MIR64-DAG:     $x{{[0-9]+}} = LI8 64
+; MIR64-DAG:     $v26 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.1)
+; MIR64-DAG:     $x{{[0-9]+}} = LI8 160
+; MIR64-DAG:     $v31 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.0)
+; MIR64-DAG:     $x{{[0-9]+}} = LI8 240
+; MIR64-DAG:     $x1 = ADDI8 $x1, 544
+; MIR64-DAG:     BLR8 implicit $lr8, implicit $rm
+
+; ASM32-LABEL:   .fprs_gprs_vecregs:
+
+; ASM32:         stwu 1, -448(1)
+; ASM32-DAG:     li {{[0-9]+}}, 32
+; ASM32-DAG:     stw 14, 232(1)                          # 4-byte Folded Spill
+; ASM32-DAG:     stfd 14, 304(1)                         # 8-byte Folded Spill
+; ASM32-DAG:     stxvd2x 52, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM32-DAG:     li {{[0-9]+}}, 128
+; ASM32-DAG:     stw 25, 276(1)                          # 4-byte Folded Spill
+; ASM32-DAG:     stxvd2x 58, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM32-DAG:     li {{[0-9]+}}, 208
+; ASM32-DAG:     stw 31, 300(1)                          # 4-byte Folded Spill
+; ASM32-DAG:     stfd 21, 360(1)                         # 8-byte Folded Spill
+; ASM32-DAG:     stfd 31, 440(1)                         # 8-byte Folded Spill
+; ASM32-DAG:     stxvd2x 63, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM32-DAG:     #APP
+; ASM32-DAG:     #NO_APP
+; ASM32-DAG:     lxvd2x 63, 1, {{[0-9]+}}                # 16-byte Folded Reload
+; ASM32-DAG:     li {{[0-9]+}}, 128
+; ASM32-DAG:     lfd 31, 440(1)                          # 8-byte Folded Reload
+; ASM32-DAG:     lxvd2x 58, 1, {{[0-9]+}}                # 16-byte Folded Reload
+; ASM32-DAG:     li {{[0-9]+}}, 32
+; ASM32-DAG:     lfd 21, 360(1)                          # 8-byte Folded Reload
+; ASM32-DAG:     lxvd2x 52, 1, {{[0-9]+}}                # 16-byte Folded Reload
+; ASM32-DAG:     lfd 14, 304(1)                          # 8-byte Folded Reload
+; ASM32-DAG:     lwz 31, 300(1)                          # 4-byte Folded Reload
+; ASM32-DAG:     lwz 25, 276(1)                          # 4-byte Folded Reload
+; ASM32-DAG:     lwz 14, 232(1)                          # 4-byte Folded Reload
+; ASM32-DAG:     addi 1, 1, 448
+; ASM32:         blr
+
+; ASM64-LABEL    .fprs_gprs_vecregs:
+
+; ASM64:         stdu 1, -544(1)
+; ASM64-DAG:     li {{[0-9]+}}, 64
+; ASM64-DAG:     std 14, 256(1)                          # 8-byte Folded Spill
+; ASM64-DAG:     stfd 14, 400(1)                         # 8-byte Folded Spill
+; ASM64-DAG:     stxvd2x 52, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM64-DAG:     li {{[0-9]+}}, 160
+; ASM64-DAG:     std 25, 344(1)                          # 8-byte Folded Spill
+; ASM64-DAG:     stxvd2x 58, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM64-DAG:     li {{[0-9]+}}, 240
+; ASM64-DAG:     std 31, 392(1)                          # 8-byte Folded Spill
+; ASM64-DAG:     stfd 21, 456(1)                         # 8-byte Folded Spill
+; ASM64-DAG:     stfd 31, 536(1)                         # 8-byte Folded Spill
+; ASM64-DAG:     stxvd2x 63, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM64-DAG:     #APP
+; ASM64-DAG:     #NO_APP
+; ASM64-DAG:     lxvd2x 63, 1, {{[0-9]+}}                # 16-byte Folded Reload
+; ASM64-DAG:     li {{[0-9]+}}, 160
+; ASM64-DAG:     lfd 31, 536(1)                          # 8-byte Folded Reload
+; ASM64-DAG:     lxvd2x 58, 1, {{[0-9]+}}                # 16-byte Folded Reload
+; ASM64-DAG:     li {{[0-9]+}}, 64
+; ASM64-DAG:     lfd 21, 456(1)                          # 8-byte Folded Reload
+; ASM64-DAG:     lxvd2x 52, 1, {{[0-9]+}}                # 16-byte Folded Reload
+; ASM64-DAG:     lfd 14, 400(1)                          # 8-byte Folded Reload
+; ASM64-DAG:     ld 31, 392(1)                           # 8-byte Folded Reload
+; ASM64-DAG:     ld 25, 344(1)                           # 8-byte Folded Reload
+; ASM64-DAG:     ld 14, 256(1)                           # 8-byte Folded Reload
+; ASM64-DAG:     addi 1, 1, 544
+; ASM64:         blr

diff --git a/llvm/test/CodeGen/PowerPC/aix-func-align.ll b/llvm/test/CodeGen/PowerPC/aix-func-align.ll
index 6d69a4f..2e7ea17 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-func-align.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-func-align.ll
@@ -1,9 +1,9 @@
 ; This test tries to verify if a csect containing code would have the correct alignment.
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYMS %s
 
 ; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \

diff --git a/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll b/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
index 27cd5b5..e87f9e7 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj  --symbols %t.o | FileCheck %s
 
 define void @foo() {

diff --git a/llvm/test/CodeGen/PowerPC/aix-internal.ll b/llvm/test/CodeGen/PowerPC/aix-internal.ll
index 1a1fb78..6f3ce85 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-internal.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-internal.ll
@@ -1,7 +1,7 @@
-; RUN: llc -mtriple powerpc-ibm-aix -verify-machineinstrs -mcpu=pwr4  \
+; RUN: llc -mtriple powerpc-ibm-aix -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
 ; RUN: -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --syms %t.o | FileCheck %s
-; RUN: not --crash llc -mtriple powerpc64-ibm-aix -verify-machineinstrs -mcpu=pwr4 \
+; RUN: not --crash llc -mtriple powerpc64-ibm-aix -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
 ; RUN: -filetype=obj -o %t.o < %s 2>&1 | FileCheck --check-prefix=64-CHECK %s
 
 define internal i32 @foo() {

diff --git a/llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll b/llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll
index 4db879a..73452d5 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll
@@ -1,29 +1,29 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32SMALL-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32LARGE-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64SMALL-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64LARGE-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck --check-prefixes=32SMALL-ASM,SMALL-ASM %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck --check-prefixes=32LARGE-ASM,LARGE-ASM %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck --check-prefixes=64SMALL-ASM,SMALL-ASM %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck --check-prefixes=64LARGE-ASM,LARGE-ASM %s
 
 define void @foo() {

diff --git a/llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll b/llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll
index d125b89..c774412 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll
@@ -1,29 +1,29 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32SMALL-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32LARGE-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64SMALL-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64LARGE-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck --check-prefixes=32SMALL-ASM,SMALL-ASM %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck --check-prefixes=32LARGE-ASM,LARGE-ASM %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck --check-prefixes=64SMALL-ASM,SMALL-ASM %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck --check-prefixes=64LARGE-ASM,LARGE-ASM %s
 
 define float @test_float() {

diff --git a/llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll b/llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
index 78ef175..ec3d9c3 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
@@ -1,16 +1,16 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32SMALL-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32LARGE-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64SMALL-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64LARGE-MIR %s
 

diff --git a/llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll b/llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
index 72661bf..0bb393b 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
@@ -1,6 +1,6 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN:     -data-sections=false < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN:     -data-sections=false < %s | FileCheck --check-prefix=CHECK64 %s
 
 @foo_ptr = global void (...)* @foo

diff --git a/llvm/test/CodeGen/PowerPC/aix-return55.ll b/llvm/test/CodeGen/PowerPC/aix-return55.ll
index 344437c..83d95fc 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-return55.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-return55.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mcpu=pwr4 -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false < %s | FileCheck %s
-; RUN: llc -mcpu=pwr4 -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llc -mcpu=pwr4 -mattr=-altivec -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false < %s | FileCheck %s
+; RUN: llc -mcpu=pwr4 -mattr=-altivec -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -sections %t.o | FileCheck --check-prefix=CHECKSECT %s
 

diff --git a/llvm/test/CodeGen/PowerPC/aix-space.ll b/llvm/test/CodeGen/PowerPC/aix-space.ll
index d681d63..27a8767 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-space.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-space.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
 
 @a = common global double 0.000000e+00, align 8
 

diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll
index 3d72a4b..708177f 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll
@@ -1,26 +1,26 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -data-sections < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff -data-sections < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -data-sections -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -data-sections -o %t.o < %s
 ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 ;; Test to see if the default is correct for -data-sections on AIX.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 ;; Test to see if the default is correct for -data-sections on AIX.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 

diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll
index 5e8c155..643e881 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll
@@ -1,6 +1,6 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 

diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
index 0cf2022..dbb3349 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
@@ -1,10 +1,10 @@
 ; This file tests the codegen of mergeable const in AIX assembly.
 ; This file also tests mergeable const in XCOFF object file generation.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections=false < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 

diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll
index f4fe274..3cb860d 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll
@@ -3,12 +3,12 @@
 ; the test in this file should be merged into aix-xcoff-data.ll with additional
 ; tests for XCOFF object files.
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
 ; RUN:     -mtriple powerpc-ibm-aix-xcoff  -data-sections=false < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
 ; RUN:     -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | FileCheck %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s
 
 @magic16 = private unnamed_addr constant [4 x i16] [i16 264, i16 272, i16 213, i16 0], align 2

diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll
index 18aea72..0f2c0ed 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN:     -filetype=obj -code-model=large -o %t.o < %s
 ; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefixes=RELOC %s
 ; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s

diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll
index d68fe8b..5410b03 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o  < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o  < %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECK %s
 
 define i32 @foo() #0 {

diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
index 5fa60f4..730fdad 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
@@ -1,12 +1,12 @@
 ; This file tests TOC entry generation and undefined symbol generation.
 
-; RUN: llc  -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefixes CHECK,CHECK32 %s
-; RUN: llc  -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck --check-prefixes CHECK,CHECK64  %s
+; RUN: llc  -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefixes CHECK,CHECK32 %s
+; RUN: llc  -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck --check-prefixes CHECK,CHECK64  %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s
 
-; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o 2>&1 \
+; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o 2>&1 \
 ; RUN: < %s | FileCheck --check-prefix=XCOFF64 %s
 ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
 

diff --git a/llvm/test/CodeGen/PowerPC/aix32-crsave.mir b/llvm/test/CodeGen/PowerPC/aix32-crsave.mir
index 8faf102..5622c96 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix32-crsave.mir
+++ b/llvm/test/CodeGen/PowerPC/aix32-crsave.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple powerpc-unknown-aix-xcoff -x mir -mcpu=pwr4 \
+# RUN: llc -mtriple powerpc-unknown-aix-xcoff -x mir -mcpu=pwr4 -mattr=-altivec \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK
 

diff --git a/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll b/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
index 04aa0d5..a068059 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
+++ b/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE
 
 @a = common global i32 0

diff --git a/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll b/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
index 14c24f0..54b1480 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
+++ b/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE
 
 @a = common global i32 0

diff --git a/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll b/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
index e2fead9..5a7e4c2 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
+; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \
 ; RUN: -mtriple=powerpc-ibm-aix-xcoff 2>&1 | FileCheck %s
 
-; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
+; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \
 ; RUN: -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
 
 ; When we convert an `i64` to `f32` on 32-bit PPC target, a `setcc` will be

diff --git a/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir b/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
index b7c0b7e..e6a29a7 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
+++ b/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
@@ -1,13 +1,13 @@
-# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -x mir -mcpu=pwr8 \
+# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -x mir -mcpu=pwr8 -mattr=-altivec \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEONE
 
-# RUN: llc -mtriple powerpc64-unknown-linux-gnu -x mir -mcpu=pwr7 \
+# RUN: llc -mtriple powerpc64-unknown-linux-gnu -x mir -mcpu=pwr7 -mattr=-altivec \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
 
-# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 \
+# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 -mattr=-altivec \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL