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powerpc/mpc8xxx: Remove P1015 and P1016 from CPU list
authorYork Sun <yorksun@freescale.com>
Fri, 10 Aug 2012 11:07:26 +0000 (11:07 +0000)
committerAndy Fleming <afleming@freescale.com>
Thu, 23 Aug 2012 15:24:16 +0000 (10:24 -0500)
P1015 is the same as P1011 and P1016 is the same as P1012 from software
point of view. They have different packages but share SVRs.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
arch/powerpc/cpu/mpc85xx/Makefile patch | blob | history
arch/powerpc/cpu/mpc85xx/speed.c patch | blob | history
arch/powerpc/cpu/mpc8xxx/cpu.c patch | blob | history
arch/powerpc/include/asm/config_mpc85xx.h patch | blob | history
arch/powerpc/include/asm/immap_85xx.h patch | blob | history
arch/powerpc/include/asm/processor.h patch | blob | history
drivers/qe/uec.c patch | blob | history

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 34f6c54..2f79a03 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -55,8 +55,6 @@ COBJS-$(CONFIG_P1011) += ddr-gen3.o
 COBJS-$(CONFIG_P1012)  += ddr-gen3.o
 COBJS-$(CONFIG_P1013)  += ddr-gen3.o
 COBJS-$(CONFIG_P1014)  += ddr-gen3.o
-COBJS-$(CONFIG_P1015)  += ddr-gen3.o
-COBJS-$(CONFIG_P1016)  += ddr-gen3.o
 COBJS-$(CONFIG_P1020)  += ddr-gen3.o
 COBJS-$(CONFIG_P1021)  += ddr-gen3.o
 COBJS-$(CONFIG_P1022)  += ddr-gen3.o
@@ -103,8 +101,6 @@ COBJS-$(CONFIG_P1011)       += p1021_serdes.o
 COBJS-$(CONFIG_P1012)  += p1021_serdes.o
 COBJS-$(CONFIG_P1013)  += p1022_serdes.o
 COBJS-$(CONFIG_P1014)  += p1010_serdes.o
-COBJS-$(CONFIG_P1015)  += p1021_serdes.o
-COBJS-$(CONFIG_P1016)  += p1021_serdes.o
 COBJS-$(CONFIG_P1017)  += p1023_serdes.o
 COBJS-$(CONFIG_P1020)  += p1021_serdes.o
 COBJS-$(CONFIG_P1021)  += p1021_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index ce47532..abfeb26 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -186,8 +186,7 @@ void get_sys_info (sys_info_t * sysInfo)
 #endif
 
 #ifdef CONFIG_QE
-#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
-    defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
        sysInfo->freqQE =  sysInfo->freqSystemBus;
 #else
        qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index cbc6742..1c615d0 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -57,8 +57,6 @@ struct cpu_type cpu_type_list [] = {
        CPU_TYPE_ENTRY(P1012, P1012, 1),
        CPU_TYPE_ENTRY(P1013, P1013, 1),
        CPU_TYPE_ENTRY(P1014, P1014, 1),
-       CPU_TYPE_ENTRY(P1015, P1015, 1),
-       CPU_TYPE_ENTRY(P1016, P1016, 1),
        CPU_TYPE_ENTRY(P1017, P1017, 1),
        CPU_TYPE_ENTRY(P1020, P1020, 2),
        CPU_TYPE_ENTRY(P1021, P1021, 2),
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 7e61f71..0a780d7 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -191,33 +191,6 @@
 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 
-/* P1015 is single core version of P1024 */
-#elif defined(CONFIG_P1015)
-#define CONFIG_MAX_CPUS                        1
-#define CONFIG_SYS_FSL_NUM_LAWS                12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
-#define CONFIG_TSECV2
-#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT      2
-#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-
-/* P1016 is single core version of P1025 */
-#elif defined(CONFIG_P1016)
-#define CONFIG_MAX_CPUS                        1
-#define CONFIG_SYS_FSL_NUM_LAWS                12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB  2
-#define CONFIG_TSECV2
-#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT      2
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define QE_MURAM_SIZE                  0x6000UL
-#define MAX_QE_RISC                    1
-#define QE_NUM_OF_SNUM                 28
-#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
-
 /* P1017 is single core version of P1023 */
 #elif defined(CONFIG_P1017)
 #define CONFIG_MAX_CPUS                        1
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 91228e7..83f8813 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2260,8 +2260,7 @@ typedef struct ccsr_gur {
        u8      res11a[76];
        par_io_t qe_par_io[7];
        u8      res11b[1600];
-#elif defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
-      defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
        u8      res11a[12];
        u32     iovselsr;
        u8      res11b[60];
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index dc009d6..095b99f 100644 (file)
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1075,8 +1075,6 @@
 #define SVR_P1012      0x80E501
 #define SVR_P1013      0x80E700
 #define SVR_P1014      0x80F101
-#define SVR_P1015      0x80E502
-#define SVR_P1016      0x80E503
 #define SVR_P1017      0x80F700
 #define SVR_P1020      0x80E400
 #define SVR_P1021      0x80E401
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 216c898..e6ae709 100644 (file)
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -580,8 +580,7 @@ static void phy_change(struct eth_device *dev)
 {
        uec_private_t   *uec = (uec_private_t *)dev->priv;
 
-#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
-    defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
        /* QE9 and QE12 need to be set for enabling QE MII managment signals */
@@ -592,8 +591,7 @@ static void phy_change(struct eth_device *dev)
        /* Update the link, speed, duplex */
        uec->mii_info->phyinfo->read_status(uec->mii_info);
 
-#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
-    defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
        /*
         * QE12 is muxed with LBCTL, it needs to be released for enabling
         * LBCTL signal for LBC usage.
@@ -1208,16 +1206,14 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
        uec_private_t           *uec;
        int                     err, i;
        struct phy_info         *curphy;
-#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
-    defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 
        uec = (uec_private_t *)dev->priv;
 
        if (uec->the_first_run == 0) {
-#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
-    defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
        /* QE9 and QE12 need to be set for enabling QE MII managment signals */
        setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
        setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
@@ -1249,8 +1245,7 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
                        udelay(100000);
                } while (1);
 
-#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
-    defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
                /* QE12 needs to be released for enabling LBCTL signal*/
                clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
 #endif
Domain: System / Kernel;