clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries

Add SSIF-2{0,1,2,3} clock and reset entries in CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425095244.156720-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index 961216d..d54bccf 100644 (file)
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -144,6 +144,22 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
                                0x554, 6),
        DEF_MOD("sdhi1_aclk",   R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1,
                                0x554, 7),
+       DEF_MOD("ssi0_pclk",    R9A07G043_SSI0_PCLK2, R9A07G043_CLK_P0,
+                               0x570, 0),
+       DEF_MOD("ssi0_sfr",     R9A07G043_SSI0_PCLK_SFR, R9A07G043_CLK_P0,
+                               0x570, 1),
+       DEF_MOD("ssi1_pclk",    R9A07G043_SSI1_PCLK2, R9A07G043_CLK_P0,
+                               0x570, 2),
+       DEF_MOD("ssi1_sfr",     R9A07G043_SSI1_PCLK_SFR, R9A07G043_CLK_P0,
+                               0x570, 3),
+       DEF_MOD("ssi2_pclk",    R9A07G043_SSI2_PCLK2, R9A07G043_CLK_P0,
+                               0x570, 4),
+       DEF_MOD("ssi2_sfr",     R9A07G043_SSI2_PCLK_SFR, R9A07G043_CLK_P0,
+                               0x570, 5),
+       DEF_MOD("ssi3_pclk",    R9A07G043_SSI3_PCLK2, R9A07G043_CLK_P0,
+                               0x570, 6),
+       DEF_MOD("ssi3_sfr",     R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0,
+                               0x570, 7),
        DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0,
                                0x57c, 0),
        DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT,
@@ -186,6 +202,10 @@ static struct rzg2l_reset r9a07g043_resets[] = {
        DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1),
        DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
        DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
+       DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0),
+       DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1),
+       DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2),
+       DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3),
        DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0),
        DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1),
        DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0),