rates from 10GE to 100GE. This could be present in some of the Xilinx
Versal designs.
+config VSC7385_ENET
+ bool "Vitesse 7385 Switch Firmware Upload driver"
+
+config VSC9953
+ bool "Vitesse VSC9953 L2 Switch driver"
+
config XILINX_EMACLITE
select PHYLIB
select MII
/* Enable VSC9953 L2 Switch driver on T1040 SoC */
#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
-#define CONFIG_VSC9953
#ifdef CONFIG_TARGET_T1040RDB
#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
#include <linux/stringify.h>
#if defined(CONFIG_TARGET_P1020RDB_PC)
-#define CONFIG_VSC7385_ENET
#define CONFIG_SLIC
#define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0x5c
* 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
*/
#if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_VSC7385_ENET
#define CONFIG_SLIC
#define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0x64
#endif
#if defined(CONFIG_TARGET_P2020RDB)
-#define CONFIG_VSC7385_ENET
#define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0xc8
#define __SW_BOOT_SPI 0x28