if (sourceNo)
diag << "Region #" << sourceNo.getValue();
else
- diag << op->getName();
+ diag << "parent operands";
diag << " to ";
if (succRegionNo)
diag << "Region #" << succRegionNo.getValue();
else
- diag << op->getName();
+ diag << "parent results";
return diag;
};
TypeRange succInputsTypes = succ.getSuccessorInputs().getTypes();
if (sourceTypes.size() != succInputsTypes.size()) {
InFlightDiagnostic diag = op->emitOpError(" region control flow edge ");
- return printEdgeName(diag)
- << " has " << sourceTypes.size()
- << " source operands, but target successor needs "
- << succInputsTypes.size();
+ return printEdgeName(diag) << ": source has " << sourceTypes.size()
+ << " operands, but target successor needs "
+ << succInputsTypes.size();
}
for (auto typesIdx :
if (sourceType != inputType) {
InFlightDiagnostic diag = op->emitOpError(" along control flow edge ");
return printEdgeName(diag)
- << " source #" << typesIdx.index() << " type " << sourceType
- << " should match input #" << typesIdx.index() << " type "
+ << ": source type #" << typesIdx.index() << " " << sourceType
+ << " should match input type #" << typesIdx.index() << " "
<< inputType;
}
}
func @std_if_incorrect_yield(%arg0: i1, %arg1: f32)
{
- // expected-error@+1 {{region control flow edge from Region #0 to scf.if has 1 source operands, but target successor needs 2}}
+ // expected-error@+1 {{region control flow edge from Region #0 to parent results: source has 1 operands, but target successor needs 2}}
%x, %y = scf.if %arg0 -> (f32, f32) {
%0 = addf %arg1, %arg1 : f32
scf.yield %0 : f32
func @std_for_operands_mismatch_4(%arg0 : index, %arg1 : index, %arg2 : index) {
%s0 = constant 0.0 : f32
%t0 = constant 1.0 : f32
- // expected-error @+1 {{along control flow edge from Region #0 to Region #0 source #1 type 'i32' should match input #1 type 'f32'}}
+ // expected-error @+1 {{along control flow edge from Region #0 to Region #0: source type #1 'i32' should match input type #1 'f32'}}
%result1:2 = scf.for %i0 = %arg0 to %arg1 step %arg2
iter_args(%si = %s0, %ti = %t0) -> (f32, f32) {
%sn = addf %si, %si : f32