Additionally, verify that the register defined by the producer is a
32-bit register.
llvm-svn: 324381
if (QII->isSolo(*II))
return false;
+ if (QII->isFloat(*II))
+ return false;
+
+ // Make sure that the (unique) def operand is a register from IntRegs.
+ bool HadDef = false;
+ for (const MachineOperand &Op : II->operands()) {
+ if (!Op.isReg() || !Op.isDef())
+ continue;
+ if (HadDef)
+ return false;
+ HadDef = true;
+ if (!Hexagon::IntRegsRegClass.contains(Op.getReg()))
+ return false;
+ }
+ assert(HadDef);
+
// Make sure there there is no 'def' or 'use' of any of the uses of
// feeder insn between it's definition, this MI and jump, jmpInst
// skipping compare, cmpInst.
--- /dev/null
+# RUN: llc -march=hexagon -run-pass=hexagon-nvj %s -o - | FileCheck %s
+
+# Check that we don't generate a new-value jump for a floating-point
+# instruction.
+# CHECK-NOT: J4_cmpgti_t_jumpnv_t
+
+---
+name: fred
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $d0
+ $r0 = F2_conv_df2w_chop $d0, implicit $usr
+ $p0 = C2_cmpgti $r0, 30
+ J2_jumpt $p0, %bb.1, implicit-def $pc
+ bb.1:
+ J2_jumpr $r31, implicit-def $pc
+...
+