Add m32r support.
authorDoug Evans <dje@gnu.org>
Mon, 24 Mar 1997 21:11:18 +0000 (21:11 +0000)
committerDoug Evans <dje@gnu.org>
Mon, 24 Mar 1997 21:11:18 +0000 (21:11 +0000)
From-SVN: r13784

gcc/longlong.h

index 65a7179..02cc75c 100644 (file)
     __w; })  
 #endif /* __i960__ */
 
+#if defined (__M32R__)
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  /* The cmp clears the condition bit.  */ \
+  __asm__ ("cmp %0,%0
+       addx %%5,%1
+       addx %%3,%0"                                                    \
+          : "=r" ((USItype) (sh)),                                     \
+            "=&r" ((USItype) (sl))                                     \
+          : "%0" ((USItype) (ah)),                                     \
+            "r" ((USItype) (bh)),                                      \
+            "%1" ((USItype) (al)),                                     \
+            "r" ((USItype) (bl))                                       \
+          : "cbit")
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  /* The cmp clears the condition bit.  */ \
+  __asm__ ("cmp %0,%0
+       subx %5,%1
+       subx %3,%0"                                                     \
+          : "=r" ((USItype) (sh)),                                     \
+            "=&r" ((USItype) (sl))                                     \
+          : "0" ((USItype) (ah)),                                      \
+            "r" ((USItype) (bh)),                                      \
+            "1" ((USItype) (al)),                                      \
+            "r" ((USItype) (bl))                                       \
+          : "cbit")
+#endif /* __M32R__ */
+
 #if defined (__mc68000__)
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add%.l %5,%1