MIPS: PMC-Sierra Yosemite: Remove support.
authorRalf Baechle <ralf@linux-mips.org>
Tue, 11 Dec 2012 20:02:55 +0000 (21:02 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Thu, 13 Dec 2012 17:15:30 +0000 (18:15 +0100)
Nobody seems to be interested anymore and upstream also never had an
ethernet driver.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
72 files changed:
arch/mips/Kconfig
arch/mips/Makefile
arch/mips/configs/yosemite_defconfig [deleted file]
arch/mips/include/asm/hazards.h
arch/mips/include/asm/mach-ar7/war.h
arch/mips/include/asm/mach-ath79/war.h
arch/mips/include/asm/mach-au1x00/war.h
arch/mips/include/asm/mach-bcm47xx/war.h
arch/mips/include/asm/mach-bcm63xx/war.h
arch/mips/include/asm/mach-cavium-octeon/war.h
arch/mips/include/asm/mach-cobalt/war.h
arch/mips/include/asm/mach-dec/war.h
arch/mips/include/asm/mach-emma2rh/war.h
arch/mips/include/asm/mach-generic/irq.h
arch/mips/include/asm/mach-ip22/war.h
arch/mips/include/asm/mach-ip27/war.h
arch/mips/include/asm/mach-ip28/war.h
arch/mips/include/asm/mach-ip32/war.h
arch/mips/include/asm/mach-jazz/war.h
arch/mips/include/asm/mach-jz4740/war.h
arch/mips/include/asm/mach-lantiq/war.h
arch/mips/include/asm/mach-lasat/war.h
arch/mips/include/asm/mach-loongson/war.h
arch/mips/include/asm/mach-loongson1/war.h
arch/mips/include/asm/mach-malta/war.h
arch/mips/include/asm/mach-netlogic/war.h
arch/mips/include/asm/mach-pnx833x/war.h
arch/mips/include/asm/mach-pnx8550/war.h
arch/mips/include/asm/mach-powertv/war.h
arch/mips/include/asm/mach-rc32434/war.h
arch/mips/include/asm/mach-rm/war.h
arch/mips/include/asm/mach-sead3/war.h
arch/mips/include/asm/mach-sibyte/war.h
arch/mips/include/asm/mach-tx39xx/war.h
arch/mips/include/asm/mach-tx49xx/war.h
arch/mips/include/asm/mach-vr41xx/war.h
arch/mips/include/asm/mach-wrppmc/war.h
arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h [deleted file]
arch/mips/include/asm/mach-yosemite/war.h [deleted file]
arch/mips/include/asm/mipsregs.h
arch/mips/include/asm/mmu_context.h
arch/mips/include/asm/module.h
arch/mips/include/asm/pgtable-bits.h
arch/mips/include/asm/pmc-sierra/msp71xx/war.h
arch/mips/include/asm/titan_dep.h [deleted file]
arch/mips/include/asm/war.h
arch/mips/kernel/Makefile
arch/mips/kernel/irq-rm9000.c [deleted file]
arch/mips/mm/c-r4k.c
arch/mips/mm/page.c
arch/mips/mm/tlbex.c
arch/mips/oprofile/Makefile
arch/mips/oprofile/common.c
arch/mips/oprofile/op_model_rm9000.c [deleted file]
arch/mips/pci/Makefile
arch/mips/pci/fixup-yosemite.c [deleted file]
arch/mips/pci/ops-titan-ht.c [deleted file]
arch/mips/pci/ops-titan.c [deleted file]
arch/mips/pci/pci-yosemite.c [deleted file]
arch/mips/pmc-sierra/Kconfig
arch/mips/pmc-sierra/Platform
arch/mips/pmc-sierra/yosemite/Makefile [deleted file]
arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c [deleted file]
arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h [deleted file]
arch/mips/pmc-sierra/yosemite/ht-irq.c [deleted file]
arch/mips/pmc-sierra/yosemite/ht.c [deleted file]
arch/mips/pmc-sierra/yosemite/irq.c [deleted file]
arch/mips/pmc-sierra/yosemite/prom.c [deleted file]
arch/mips/pmc-sierra/yosemite/py-console.c [deleted file]
arch/mips/pmc-sierra/yosemite/setup.c [deleted file]
arch/mips/pmc-sierra/yosemite/setup.h [deleted file]
arch/mips/pmc-sierra/yosemite/smp.c [deleted file]

index 53470f0..9806a5a 100644 (file)
@@ -416,27 +416,6 @@ config PMC_MSP
          of integrated peripherals, interfaces and DSPs in addition to
          a variety of MIPS cores.
 
-config PMC_YOSEMITE
-       bool "PMC-Sierra Yosemite eval board"
-       select CEVT_R4K
-       select CSRC_R4K
-       select DMA_COHERENT
-       select HW_HAS_PCI
-       select IRQ_CPU
-       select IRQ_CPU_RM7K
-       select IRQ_CPU_RM9K
-       select SWAP_IO_SPACE
-       select SYS_HAS_CPU_RM9000
-       select SYS_HAS_EARLY_PRINTK
-       select SYS_SUPPORTS_32BIT_KERNEL
-       select SYS_SUPPORTS_64BIT_KERNEL
-       select SYS_SUPPORTS_BIG_ENDIAN
-       select SYS_SUPPORTS_HIGHMEM
-       select SYS_SUPPORTS_SMP
-       help
-         Yosemite is an evaluation board for the RM9000x2 processor
-         manufactured by PMC-Sierra.
-
 config POWERTV
        bool "Cisco PowerTV"
        select BOOT_ELF32
@@ -1080,9 +1059,6 @@ config IRQ_CPU
 config IRQ_CPU_RM7K
        bool
 
-config IRQ_CPU_RM9K
-       bool
-
 config IRQ_MSP_SLP
        bool
 
@@ -1107,10 +1083,6 @@ config PCI_GT64XXX_PCI0
 config NO_EXCEPT_FILL
        bool
 
-config MIPS_RM9122
-       bool
-       select SERIAL_RM9000
-
 config SOC_EMMA2RH
        bool
        select CEVT_R4K
@@ -1156,9 +1128,6 @@ config SOC_PNX8550
 config SWAP_IO_SPACE
        bool
 
-config SERIAL_RM9000
-       bool
-
 config SGI_HAS_INDYDOG
        bool
 
@@ -1452,16 +1421,6 @@ config CPU_RM7000
        select CPU_SUPPORTS_HIGHMEM
        select CPU_SUPPORTS_HUGEPAGES
 
-config CPU_RM9000
-       bool "RM9000"
-       depends on SYS_HAS_CPU_RM9000
-       select CPU_HAS_PREFETCH
-       select CPU_SUPPORTS_32BIT_KERNEL
-       select CPU_SUPPORTS_64BIT_KERNEL
-       select CPU_SUPPORTS_HIGHMEM
-       select CPU_SUPPORTS_HUGEPAGES
-       select WEAK_ORDERING
-
 config CPU_SB1
        bool "SB1"
        depends on SYS_HAS_CPU_SB1
@@ -1680,9 +1639,6 @@ config SYS_HAS_CPU_R10000
 config SYS_HAS_CPU_RM7000
        bool
 
-config SYS_HAS_CPU_RM9000
-       bool
-
 config SYS_HAS_CPU_SB1
        bool
 
index f5f873e..f2dfd40 100644 (file)
@@ -145,8 +145,6 @@ cflags-$(CONFIG_CPU_NEVADA) += $(call cc-option,-march=rm5200,-march=r5000) \
                        -Wa,--trap
 cflags-$(CONFIG_CPU_RM7000)    += $(call cc-option,-march=rm7000,-march=r5000) \
                        -Wa,--trap
-cflags-$(CONFIG_CPU_RM9000)    += $(call cc-option,-march=rm9000,-march=r5000) \
-                       -Wa,--trap
 cflags-$(CONFIG_CPU_SB1)       += $(call cc-option,-march=sb1,-march=r5000) \
                        -Wa,--trap
 cflags-$(CONFIG_CPU_R8000)     += -march=r8000 -Wa,--trap
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
deleted file mode 100644 (file)
index f72d305..0000000
+++ /dev/null
@@ -1,94 +0,0 @@
-CONFIG_PMC_YOSEMITE=y
-CONFIG_HIGHMEM=y
-CONFIG_SMP=y
-CONFIG_NR_CPUS=2
-CONFIG_HZ_1000=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_RELAY=y
-CONFIG_EXPERT=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_PCI=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=m
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=m
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_NETWORK_SECMARK=y
-CONFIG_FW_LOADER=m
-CONFIG_CONNECTOR=m
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_ATA_OVER_ETH=m
-CONFIG_SGI_IOC4=m
-CONFIG_RAID_ATTRS=m
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=m
-CONFIG_MARVELL_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_CICADA_PHY=m
-CONFIG_VITESSE_PHY=m
-CONFIG_SMSC_PHY=m
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_QLA3XXX=m
-CONFIG_CHELSIO_T3=m
-CONFIG_NETXEN_NIC=m
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-CONFIG_FUSE_FS=m
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-CONFIG_KEYS=y
-CONFIG_KEYS_DEBUG_PROC_KEYS=y
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_CAMELLIA=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRC16=m
-CONFIG_CRC32=m
-CONFIG_LIBCRC32C=m
index b4c20e4..f0324e9 100644 (file)
@@ -161,31 +161,6 @@ ASMMACRO(back_to_back_c0_hazard,
        )
 #define instruction_hazard() do { } while (0)
 
-#elif defined(CONFIG_CPU_RM9000)
-
-/*
- * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
- * use of the JTLB for instructions should not occur for 4 cpu cycles and use
- * for data translations should not occur for 3 cpu cycles.
- */
-
-ASMMACRO(mtc0_tlbw_hazard,
-        _ssnop; _ssnop; _ssnop; _ssnop
-       )
-ASMMACRO(tlbw_use_hazard,
-        _ssnop; _ssnop; _ssnop; _ssnop
-       )
-ASMMACRO(tlb_probe_hazard,
-        _ssnop; _ssnop; _ssnop; _ssnop
-       )
-ASMMACRO(irq_enable_hazard,
-       )
-ASMMACRO(irq_disable_hazard,
-       )
-ASMMACRO(back_to_back_c0_hazard,
-       )
-#define instruction_hazard() do { } while (0)
-
 #elif defined(CONFIG_CPU_SB1)
 
 /*
index f4862b5..99071e5 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index 323d9f1..0bb3090 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index dd57d03..72e260d 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index 87cd465..a3d2f44 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index 8e3f3fd..05ee867 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index c4712d7..eb72b35 100644 (file)
@@ -18,7 +18,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index 97884fd..34ae404 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index ca5e2ef..d29996f 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index b660a4c..79ae82d 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index 70d9a25..e014264 100644 (file)
 #endif
 #endif
 
-#ifdef CONFIG_IRQ_CPU_RM9K
-#ifndef RM9K_CPU_IRQ_BASE
-#define RM9K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+12)
-#endif
-#endif
-
 #endif /* CONFIG_IRQ_CPU */
 
 #endif /* __ASM_MACH_GENERIC_IRQ_H */
index a44fa96..fba6405 100644 (file)
@@ -21,7 +21,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index e2ddcc9..4ee0e4b 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        1
 #define MIPS34K_MISSED_ITLB_WAR                0
index a1baafa..4821c7b 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        1
 #define MIPS34K_MISSED_ITLB_WAR                0
index d194056..7237a93 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR   1
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index 6158ee8..5b18b9a 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index 3a5bc17..9b511d3 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index 01b08ef..b6c568c 100644 (file)
@@ -16,7 +16,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
index bb1e032..741ae72 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index 4b971c3..f2570df 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index e3680a8..8fb50d0 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index 7c6931d..d068fc4 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       1
 #define MIPS_CACHE_SYNC_WAR            1
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  1
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index 22da893..2c72168 100644 (file)
@@ -18,7 +18,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index 82cd1e9..edaa06d 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index d0458dd..de8894c 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index 7ac05ec..c5651c8 100644 (file)
@@ -20,7 +20,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       1
 #define MIPS_CACHE_SYNC_WAR            1
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  1
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index 3ddf187..1bfd489 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       1
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index 948d312..a3dde98 100644 (file)
@@ -21,7 +21,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index 7c6931d..d068fc4 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       1
 #define MIPS_CACHE_SYNC_WAR            1
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  1
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index 743385d..176f5b3 100644 (file)
@@ -33,7 +33,6 @@ extern int sb1250_m3_workaround_needed(void);
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index 4338146..6a52e65 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index 39b5d11..a8e2c58 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    1
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index 56a3892..ffe31e7 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
index ac48629..e86084c 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  1
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
diff --git a/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h b/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h
deleted file mode 100644 (file)
index 56bdd32..0000000
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H
-
-/*
- * Momentum Jaguar ATX always has the RM9000 processor.
- */
-#define cpu_has_watch          1
-#define cpu_has_mips16         0
-#define cpu_has_divec          0
-#define cpu_has_vce            0
-#define cpu_has_cache_cdex_p   0
-#define cpu_has_cache_cdex_s   0
-#define cpu_has_prefetch       1
-#define cpu_has_mcheck         0
-#define cpu_has_ejtag          0
-
-#define cpu_has_llsc           1
-#define cpu_has_vtag_icache    0
-#define cpu_has_dc_aliases     0
-#define cpu_has_ic_fills_f_dc  0
-#define cpu_has_dsp            0
-#define cpu_has_dsp2           0
-#define cpu_has_mipsmt         0
-#define cpu_has_userlocal      0
-#define cpu_icache_snoops_remote_store 0
-
-#define cpu_has_nofpuex                0
-#define cpu_has_64bits         1
-
-#define cpu_has_inclusive_pcaches      0
-
-#define cpu_dcache_line_size() 32
-#define cpu_icache_line_size() 32
-#define cpu_scache_line_size() 32
-
-#define cpu_has_mips32r1       0
-#define cpu_has_mips32r2       0
-#define cpu_has_mips64r1       0
-#define cpu_has_mips64r2       0
-
-#endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-yosemite/war.h b/arch/mips/include/asm/mach-yosemite/war.h
deleted file mode 100644 (file)
index e5c6d53..0000000
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_YOSEMITE_WAR_H
-#define __ASM_MIPS_MACH_YOSEMITE_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR    0
-#define R4600_V1_HIT_CACHEOP_WAR       0
-#define R4600_V2_HIT_CACHEOP_WAR       0
-#define R5432_CP0_INTERRUPT_WAR                0
-#define BCM1250_M3_WAR                 0
-#define SIBYTE_1956_WAR                        0
-#define MIPS4K_ICACHE_REFILL_WAR       0
-#define MIPS_CACHE_SYNC_WAR            0
-#define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            1
-#define ICACHE_REFILLS_WORKAROUND_WAR  1
-#define R10000_LLSC_WAR                        0
-#define MIPS34K_MISSED_ITLB_WAR                0
-
-#endif /* __ASM_MIPS_MACH_YOSEMITE_WAR_H */
index 881b980..7e4e6f8 100644 (file)
@@ -977,10 +977,6 @@ do {                                                                       \
 #define read_c0_framemask()    __read_32bit_c0_register($21, 0)
 #define write_c0_framemask(val)        __write_32bit_c0_register($21, 0, val)
 
-/* RM9000 PerfControl performance counter control register */
-#define read_c0_perfcontrol()  __read_32bit_c0_register($22, 0)
-#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
-
 #define read_c0_diag()         __read_32bit_c0_register($22, 0)
 #define write_c0_diag(val)     __write_32bit_c0_register($22, 0, val)
 
@@ -1033,10 +1029,6 @@ do {                                                                     \
 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
 
-/* RM9000 PerfCount performance counter register */
-#define read_c0_perfcount()    __read_64bit_c0_register($25, 0)
-#define write_c0_perfcount(val)        __write_64bit_c0_register($25, 0, val)
-
 #define read_c0_ecc()          __read_32bit_c0_register($26, 0)
 #define write_c0_ecc(val)      __write_32bit_c0_register($26, 0, val)
 
index 9b02cfb..45cfa1a 100644 (file)
@@ -72,12 +72,6 @@ extern unsigned long pgd_current[];
 #define ASID_INC       0x10
 #define ASID_MASK      0xff0
 
-#elif defined(CONFIG_CPU_RM9000)
-
-#define ASID_INC       0x1
-#define ASID_MASK      0xfff
-
-/* SMTC/34K debug hack - but maybe we'll keep it */
 #elif defined(CONFIG_MIPS_MT_SMTC)
 
 #define ASID_INC       0x1
index 26137da..44b705d 100644 (file)
@@ -120,8 +120,6 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_PROC_FAMILY "R10000 "
 #elif defined CONFIG_CPU_RM7000
 #define MODULE_PROC_FAMILY "RM7000 "
-#elif defined CONFIG_CPU_RM9000
-#define MODULE_PROC_FAMILY "RM9000 "
 #elif defined CONFIG_CPU_SB1
 #define MODULE_PROC_FAMILY "SB1 "
 #elif defined CONFIG_CPU_LOONGSON1
index 9ce1ac7..f6a0439 100644 (file)
@@ -235,20 +235,6 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
 
-#elif defined(CONFIG_CPU_RM9000)
-
-#define _CACHE_WT                  (0<<_CACHE_SHIFT)
-#define _CACHE_WTWA                (1<<_CACHE_SHIFT)
-#define _CACHE_UC_B                (2<<_CACHE_SHIFT)
-#define _CACHE_WB                  (3<<_CACHE_SHIFT)
-#define _CACHE_CWBEA               (4<<_CACHE_SHIFT)
-#define _CACHE_CWB                 (5<<_CACHE_SHIFT)
-#define _CACHE_UCNB                (6<<_CACHE_SHIFT)
-#define _CACHE_FPC                 (7<<_CACHE_SHIFT)
-
-#define _CACHE_UNCACHED                    _CACHE_UC_B
-#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB
-
 #else
 
 #define _CACHE_CACHABLE_NO_WA      (0<<_CACHE_SHIFT)  /* R4600 only      */
index 9e2ee42..c74eb16 100644 (file)
@@ -17,7 +17,6 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
-#define RM9000_CDEX_SMP_WAR            0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
diff --git a/arch/mips/include/asm/titan_dep.h b/arch/mips/include/asm/titan_dep.h
deleted file mode 100644 (file)
index fee1908..0000000
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright 2003 PMC-Sierra
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- * Board specific definititions for the PMC-Sierra Yosemite
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifndef __TITAN_DEP_H__
-#define __TITAN_DEP_H__
-
-#include <asm/addrspace.h>              /* for KSEG1ADDR() */
-#include <asm/byteorder.h>              /* for cpu_to_le32() */
-
-#define TITAN_READ(ofs)                                                        \
-       (*(volatile u32 *)(ocd_base+(ofs)))
-#define TITAN_READ_16(ofs)                                             \
-       (*(volatile u16 *)(ocd_base+(ofs)))
-#define TITAN_READ_8(ofs)                                              \
-       (*(volatile u8 *)(ocd_base+(ofs)))
-
-#define TITAN_WRITE(ofs, data)                                         \
-       do { *(volatile u32 *)(ocd_base+(ofs)) = (data); } while (0)
-#define TITAN_WRITE_16(ofs, data)                                      \
-       do { *(volatile u16 *)(ocd_base+(ofs)) = (data); } while (0)
-#define TITAN_WRITE_8(ofs, data)                                       \
-       do { *(volatile u8 *)(ocd_base+(ofs)) = (data); } while (0)
-
-/*
- * PCI specific defines
- */
-#define        TITAN_PCI_0_CONFIG_ADDRESS      0x780
-#define        TITAN_PCI_0_CONFIG_DATA         0x784
-
-/*
- * HT specific defines
- */
-#define RM9000x2_HTLINK_REG            0xbb000644
-#define RM9000x2_BASE_ADDR             0xbb000000
-
-#define OCD_BASE                       0xfb000000UL
-#define OCD_SIZE                       0x3000UL
-
-extern unsigned long ocd_base;
-
-/*
- * OCD Registers
- */
-#define RM9000x2_OCD_LKB5              0x0128          /* Ethernet */
-#define RM9000x2_OCD_LKM5              0x012c
-
-#define RM9000x2_OCD_LKB7              0x0138          /* HT Region 0 */
-#define RM9000x2_OCD_LKM7              0x013c
-#define RM9000x2_OCD_LKB8              0x0140          /* HT Region 1 */
-#define RM9000x2_OCD_LKM8              0x0144
-
-#define RM9000x2_OCD_LKB9              0x0148          /* Local Bus */
-#define RM9000x2_OCD_LKM9              0x014c
-#define RM9000x2_OCD_LKB10             0x0150
-#define RM9000x2_OCD_LKM10             0x0154
-#define RM9000x2_OCD_LKB11             0x0158
-#define RM9000x2_OCD_LKM11             0x015c
-#define RM9000x2_OCD_LKB12             0x0160
-#define RM9000x2_OCD_LKM12             0x0164
-
-#define RM9000x2_OCD_LKB13             0x0168          /* Scratch RAM */
-#define RM9000x2_OCD_LKM13             0x016c
-
-#define RM9000x2_OCD_LPD0              0x0200          /* Local Bus */
-#define RM9000x2_OCD_LPD1              0x0210
-#define RM9000x2_OCD_LPD2              0x0220
-#define RM9000x2_OCD_LPD3              0x0230
-
-#define RM9000x2_OCD_HTDVID            0x0600  /* HT Device Header */
-#define RM9000x2_OCD_HTSC              0x0604
-#define RM9000x2_OCD_HTCCR             0x0608
-#define RM9000x2_OCD_HTBHL             0x060c
-#define RM9000x2_OCD_HTBAR0            0x0610
-#define RM9000x2_OCD_HTBAR1            0x0614
-#define RM9000x2_OCD_HTBAR2            0x0618
-#define RM9000x2_OCD_HTBAR3            0x061c
-#define RM9000x2_OCD_HTBAR4            0x0620
-#define RM9000x2_OCD_HTBAR5            0x0624
-#define RM9000x2_OCD_HTCBCPT           0x0628
-#define RM9000x2_OCD_HTSDVID           0x062c
-#define RM9000x2_OCD_HTXRA             0x0630
-#define RM9000x2_OCD_HTCAP1            0x0634
-#define RM9000x2_OCD_HTIL              0x063c
-
-#define RM9000x2_OCD_HTLCC             0x0640  /* HT Capability Block */
-#define RM9000x2_OCD_HTLINK            0x0644
-#define RM9000x2_OCD_HTFQREV           0x0648
-
-#define RM9000x2_OCD_HTERCTL           0x0668  /* HT Controller */
-#define RM9000x2_OCD_HTRXDB            0x066c
-#define RM9000x2_OCD_HTIMPED           0x0670
-#define RM9000x2_OCD_HTSWIMP           0x0674
-#define RM9000x2_OCD_HTCAL             0x0678
-
-#define RM9000x2_OCD_HTBAA30           0x0680
-#define RM9000x2_OCD_HTBAA54           0x0684
-#define RM9000x2_OCD_HTMASK0           0x0688
-#define RM9000x2_OCD_HTMASK1           0x068c
-#define RM9000x2_OCD_HTMASK2           0x0690
-#define RM9000x2_OCD_HTMASK3           0x0694
-#define RM9000x2_OCD_HTMASK4           0x0698
-#define RM9000x2_OCD_HTMASK5           0x069c
-
-#define RM9000x2_OCD_HTIFCTL           0x06a0
-#define RM9000x2_OCD_HTPLL             0x06a4
-
-#define RM9000x2_OCD_HTSRI             0x06b0
-#define RM9000x2_OCD_HTRXNUM           0x06b4
-#define RM9000x2_OCD_HTTXNUM           0x06b8
-
-#define RM9000x2_OCD_HTTXCNT           0x06c8
-
-#define RM9000x2_OCD_HTERROR           0x06d8
-#define RM9000x2_OCD_HTRCRCE           0x06dc
-#define RM9000x2_OCD_HTEOI             0x06e0
-
-#define RM9000x2_OCD_CRCR              0x06f0
-
-#define RM9000x2_OCD_HTCFGA            0x06f8
-#define RM9000x2_OCD_HTCFGD            0x06fc
-
-#define RM9000x2_OCD_INTMSG            0x0a00
-
-#define RM9000x2_OCD_INTPIN0           0x0a40
-#define RM9000x2_OCD_INTPIN1           0x0a44
-#define RM9000x2_OCD_INTPIN2           0x0a48
-#define RM9000x2_OCD_INTPIN3           0x0a4c
-#define RM9000x2_OCD_INTPIN4           0x0a50
-#define RM9000x2_OCD_INTPIN5           0x0a54
-#define RM9000x2_OCD_INTPIN6           0x0a58
-#define RM9000x2_OCD_INTPIN7           0x0a5c
-#define RM9000x2_OCD_SEM               0x0a60
-#define RM9000x2_OCD_SEMSET            0x0a64
-#define RM9000x2_OCD_SEMCLR            0x0a68
-
-#define RM9000x2_OCD_TKT               0x0a70
-#define RM9000x2_OCD_TKTINC            0x0a74
-
-#define RM9000x2_OCD_NMICONFIG         0x0ac0          /* Interrupts */
-#define RM9000x2_OCD_INTP0PRI          0x1a80
-#define RM9000x2_OCD_INTP1PRI          0x1a80
-#define RM9000x2_OCD_INTP0STATUS0      0x1b00
-#define RM9000x2_OCD_INTP0MASK0                0x1b04
-#define RM9000x2_OCD_INTP0SET0         0x1b08
-#define RM9000x2_OCD_INTP0CLEAR0       0x1b0c
-#define RM9000x2_OCD_INTP0STATUS1      0x1b10
-#define RM9000x2_OCD_INTP0MASK1                0x1b14
-#define RM9000x2_OCD_INTP0SET1         0x1b18
-#define RM9000x2_OCD_INTP0CLEAR1       0x1b1c
-#define RM9000x2_OCD_INTP0STATUS2      0x1b20
-#define RM9000x2_OCD_INTP0MASK2                0x1b24
-#define RM9000x2_OCD_INTP0SET2         0x1b28
-#define RM9000x2_OCD_INTP0CLEAR2       0x1b2c
-#define RM9000x2_OCD_INTP0STATUS3      0x1b30
-#define RM9000x2_OCD_INTP0MASK3                0x1b34
-#define RM9000x2_OCD_INTP0SET3         0x1b38
-#define RM9000x2_OCD_INTP0CLEAR3       0x1b3c
-#define RM9000x2_OCD_INTP0STATUS4      0x1b40
-#define RM9000x2_OCD_INTP0MASK4                0x1b44
-#define RM9000x2_OCD_INTP0SET4         0x1b48
-#define RM9000x2_OCD_INTP0CLEAR4       0x1b4c
-#define RM9000x2_OCD_INTP0STATUS5      0x1b50
-#define RM9000x2_OCD_INTP0MASK5                0x1b54
-#define RM9000x2_OCD_INTP0SET5         0x1b58
-#define RM9000x2_OCD_INTP0CLEAR5       0x1b5c
-#define RM9000x2_OCD_INTP0STATUS6      0x1b60
-#define RM9000x2_OCD_INTP0MASK6                0x1b64
-#define RM9000x2_OCD_INTP0SET6         0x1b68
-#define RM9000x2_OCD_INTP0CLEAR6       0x1b6c
-#define RM9000x2_OCD_INTP0STATUS7      0x1b70
-#define RM9000x2_OCD_INTP0MASK7                0x1b74
-#define RM9000x2_OCD_INTP0SET7         0x1b78
-#define RM9000x2_OCD_INTP0CLEAR7       0x1b7c
-#define RM9000x2_OCD_INTP1STATUS0      0x2b00
-#define RM9000x2_OCD_INTP1MASK0                0x2b04
-#define RM9000x2_OCD_INTP1SET0         0x2b08
-#define RM9000x2_OCD_INTP1CLEAR0       0x2b0c
-#define RM9000x2_OCD_INTP1STATUS1      0x2b10
-#define RM9000x2_OCD_INTP1MASK1                0x2b14
-#define RM9000x2_OCD_INTP1SET1         0x2b18
-#define RM9000x2_OCD_INTP1CLEAR1       0x2b1c
-#define RM9000x2_OCD_INTP1STATUS2      0x2b20
-#define RM9000x2_OCD_INTP1MASK2                0x2b24
-#define RM9000x2_OCD_INTP1SET2         0x2b28
-#define RM9000x2_OCD_INTP1CLEAR2       0x2b2c
-#define RM9000x2_OCD_INTP1STATUS3      0x2b30
-#define RM9000x2_OCD_INTP1MASK3                0x2b34
-#define RM9000x2_OCD_INTP1SET3         0x2b38
-#define RM9000x2_OCD_INTP1CLEAR3       0x2b3c
-#define RM9000x2_OCD_INTP1STATUS4      0x2b40
-#define RM9000x2_OCD_INTP1MASK4                0x2b44
-#define RM9000x2_OCD_INTP1SET4         0x2b48
-#define RM9000x2_OCD_INTP1CLEAR4       0x2b4c
-#define RM9000x2_OCD_INTP1STATUS5      0x2b50
-#define RM9000x2_OCD_INTP1MASK5                0x2b54
-#define RM9000x2_OCD_INTP1SET5         0x2b58
-#define RM9000x2_OCD_INTP1CLEAR5       0x2b5c
-#define RM9000x2_OCD_INTP1STATUS6      0x2b60
-#define RM9000x2_OCD_INTP1MASK6                0x2b64
-#define RM9000x2_OCD_INTP1SET6         0x2b68
-#define RM9000x2_OCD_INTP1CLEAR6       0x2b6c
-#define RM9000x2_OCD_INTP1STATUS7      0x2b70
-#define RM9000x2_OCD_INTP1MASK7                0x2b74
-#define RM9000x2_OCD_INTP1SET7         0x2b78
-#define RM9000x2_OCD_INTP1CLEAR7       0x2b7c
-
-#define OCD_READ(reg)          (*(volatile unsigned int *)(ocd_base + (reg)))
-#define OCD_WRITE(reg, val)                                    \
-       do { *(volatile unsigned int *)(ocd_base + (reg)) = (val); } while (0)
-
-/*
- * Hypertransport specific macros
- */
-#define RM9K_WRITE(ofs, data)   *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs) = data
-#define RM9K_WRITE_8(ofs, data) *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs) = data
-#define RM9K_WRITE_16(ofs, data) *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs) = data
-
-#define RM9K_READ(ofs, val)     *(val) = *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs)
-#define RM9K_READ_8(ofs, val)   *(val) = *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs)
-#define RM9K_READ_16(ofs, val)  *(val) = *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs)
-
-#endif
index fa133c1..65e3445 100644 (file)
 #endif
 
 /*
- * On the RM9000 there is a problem which makes the CreateDirtyExclusive
- * eache operation unusable on SMP systems.
- */
-#ifndef RM9000_CDEX_SMP_WAR
-#error Check setting of RM9000_CDEX_SMP_WAR for your platform
-#endif
-
-/*
  * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
  * opposes it being called that) where invalid instructions in the same
  * I-cache line worth of instructions being fetched may case spurious
index 540dff8..007c33d 100644 (file)
@@ -58,7 +58,6 @@ obj-$(CONFIG_MIPS_VPE_APSP_API)       += rtlx.o
 obj-$(CONFIG_I8259)            += i8259.o
 obj-$(CONFIG_IRQ_CPU)          += irq_cpu.o
 obj-$(CONFIG_IRQ_CPU_RM7K)     += irq-rm7000.o
-obj-$(CONFIG_IRQ_CPU_RM9K)     += irq-rm9000.o
 obj-$(CONFIG_MIPS_MSC)         += irq-msc01.o
 obj-$(CONFIG_IRQ_TXX9)         += irq_txx9.o
 obj-$(CONFIG_IRQ_GT641XX)      += irq-gt641xx.o
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
deleted file mode 100644 (file)
index 1282b9a..0000000
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * Copyright (C) 2003 Ralf Baechle
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * Handler for RM9000 extended interrupts.  These are a non-standard
- * feature so we handle them separately from standard interrupts.
- */
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <asm/irq_cpu.h>
-#include <asm/mipsregs.h>
-
-static inline void unmask_rm9k_irq(struct irq_data *d)
-{
-       set_c0_intcontrol(0x1000 << (d->irq - RM9K_CPU_IRQ_BASE));
-}
-
-static inline void mask_rm9k_irq(struct irq_data *d)
-{
-       clear_c0_intcontrol(0x1000 << (d->irq - RM9K_CPU_IRQ_BASE));
-}
-
-static inline void rm9k_cpu_irq_enable(struct irq_data *d)
-{
-       unsigned long flags;
-
-       local_irq_save(flags);
-       unmask_rm9k_irq(d);
-       local_irq_restore(flags);
-}
-
-/*
- * Performance counter interrupts are global on all processors.
- */
-static void local_rm9k_perfcounter_irq_startup(void *args)
-{
-       rm9k_cpu_irq_enable(args);
-}
-
-static unsigned int rm9k_perfcounter_irq_startup(struct irq_data *d)
-{
-       on_each_cpu(local_rm9k_perfcounter_irq_startup, d, 1);
-
-       return 0;
-}
-
-static void local_rm9k_perfcounter_irq_shutdown(void *args)
-{
-       unsigned long flags;
-
-       local_irq_save(flags);
-       mask_rm9k_irq(args);
-       local_irq_restore(flags);
-}
-
-static void rm9k_perfcounter_irq_shutdown(struct irq_data *d)
-{
-       on_each_cpu(local_rm9k_perfcounter_irq_shutdown, d, 1);
-}
-
-static struct irq_chip rm9k_irq_controller = {
-       .name = "RM9000",
-       .irq_ack = mask_rm9k_irq,
-       .irq_mask = mask_rm9k_irq,
-       .irq_mask_ack = mask_rm9k_irq,
-       .irq_unmask = unmask_rm9k_irq,
-       .irq_eoi = unmask_rm9k_irq
-};
-
-static struct irq_chip rm9k_perfcounter_irq = {
-       .name = "RM9000",
-       .irq_startup = rm9k_perfcounter_irq_startup,
-       .irq_shutdown = rm9k_perfcounter_irq_shutdown,
-       .irq_ack = mask_rm9k_irq,
-       .irq_mask = mask_rm9k_irq,
-       .irq_mask_ack = mask_rm9k_irq,
-       .irq_unmask = unmask_rm9k_irq,
-};
-
-unsigned int rm9000_perfcount_irq;
-
-EXPORT_SYMBOL(rm9000_perfcount_irq);
-
-void __init rm9k_cpu_irq_init(void)
-{
-       int base = RM9K_CPU_IRQ_BASE;
-       int i;
-
-       clear_c0_intcontrol(0x0000f000);                /* Mask all */
-
-       for (i = base; i < base + 4; i++)
-               irq_set_chip_and_handler(i, &rm9k_irq_controller,
-                                        handle_level_irq);
-
-       rm9000_perfcount_irq = base + 1;
-       irq_set_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
-                                handle_percpu_irq);
-}
index 2b61462..d2b5b0c 100644 (file)
@@ -936,7 +936,6 @@ static void __cpuinit probe_pcache(void)
        case CPU_RM7000:
                rm7k_erratum31();
 
-       case CPU_RM9000:
                icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
                c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
                c->icache.ways = 4;
@@ -947,9 +946,7 @@ static void __cpuinit probe_pcache(void)
                c->dcache.ways = 4;
                c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
 
-#if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
                c->options |= MIPS_CPU_CACHE_CDEX_P;
-#endif
                c->options |= MIPS_CPU_PREFETCH;
                break;
 
@@ -1234,7 +1231,6 @@ static void __cpuinit setup_scache(void)
                 return;
 
        case CPU_RM7000:
-       case CPU_RM9000:
 #ifdef CONFIG_RM7000_CPU_SCACHE
                rm7k_sc_init();
 #endif
index 98f530e..8e666c5 100644 (file)
@@ -140,15 +140,6 @@ static void __cpuinit set_prefetch_parameters(void)
                        pref_bias_copy_load = 256;
                        break;
 
-               case CPU_RM9000:
-                       /*
-                        * As a workaround for erratum G105 which make the
-                        * PrepareForStore hint unusable we fall back to
-                        * StoreRetained on the RM9000.  Once it is known which
-                        * versions of the RM9000 we'll be able to condition-
-                        * alize this.
-                        */
-
                case CPU_R10000:
                case CPU_R12000:
                case CPU_R14000:
index 6af62a2..69a3572 100644 (file)
@@ -603,24 +603,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
                tlbw(p);
                break;
 
-       case CPU_RM9000:
-               /*
-                * When the JTLB is updated by tlbwi or tlbwr, a subsequent
-                * use of the JTLB for instructions should not occur for 4
-                * cpu cycles and use for data translations should not occur
-                * for 3 cpu cycles.
-                */
-               uasm_i_ssnop(p);
-               uasm_i_ssnop(p);
-               uasm_i_ssnop(p);
-               uasm_i_ssnop(p);
-               tlbw(p);
-               uasm_i_ssnop(p);
-               uasm_i_ssnop(p);
-               uasm_i_ssnop(p);
-               uasm_i_ssnop(p);
-               break;
-
        case CPU_VR4111:
        case CPU_VR4121:
        case CPU_VR4122:
index 1208c28..8232dbd 100644 (file)
@@ -12,5 +12,4 @@ oprofile-$(CONFIG_CPU_MIPS32)         += op_model_mipsxx.o
 oprofile-$(CONFIG_CPU_MIPS64)          += op_model_mipsxx.o
 oprofile-$(CONFIG_CPU_R10000)          += op_model_mipsxx.o
 oprofile-$(CONFIG_CPU_SB1)             += op_model_mipsxx.o
-oprofile-$(CONFIG_CPU_RM9000)          += op_model_rm9000.o
 oprofile-$(CONFIG_CPU_LOONGSON2)       += op_model_loongson2.o
index f80480a..be387fa 100644 (file)
@@ -16,7 +16,6 @@
 #include "op_impl.h"
 
 extern struct op_mips_model op_model_mipsxx_ops __weak;
-extern struct op_mips_model op_model_rm9000_ops __weak;
 extern struct op_mips_model op_model_loongson2_ops __weak;
 
 static struct op_mips_model *model;
@@ -94,9 +93,6 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
                lmodel = &op_model_mipsxx_ops;
                break;
 
-       case CPU_RM9000:
-               lmodel = &op_model_rm9000_ops;
-               break;
        case CPU_LOONGSON2:
                lmodel = &op_model_loongson2_ops;
                break;
diff --git a/arch/mips/oprofile/op_model_rm9000.c b/arch/mips/oprofile/op_model_rm9000.c
deleted file mode 100644 (file)
index 3aa8138..0000000
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004 by Ralf Baechle
- */
-#include <linux/init.h>
-#include <linux/oprofile.h>
-#include <linux/interrupt.h>
-#include <linux/smp.h>
-
-#include "op_impl.h"
-
-#define RM9K_COUNTER1_EVENT(event)     ((event) << 0)
-#define RM9K_COUNTER1_SUPERVISOR       (1ULL    <<  7)
-#define RM9K_COUNTER1_KERNEL           (1ULL    <<  8)
-#define RM9K_COUNTER1_USER             (1ULL    <<  9)
-#define RM9K_COUNTER1_ENABLE           (1ULL    << 10)
-#define RM9K_COUNTER1_OVERFLOW         (1ULL    << 15)
-
-#define RM9K_COUNTER2_EVENT(event)     ((event) << 16)
-#define RM9K_COUNTER2_SUPERVISOR       (1ULL    << 23)
-#define RM9K_COUNTER2_KERNEL           (1ULL    << 24)
-#define RM9K_COUNTER2_USER             (1ULL    << 25)
-#define RM9K_COUNTER2_ENABLE           (1ULL    << 26)
-#define RM9K_COUNTER2_OVERFLOW         (1ULL    << 31)
-
-extern unsigned int rm9000_perfcount_irq;
-
-static struct rm9k_register_config {
-       unsigned int control;
-       unsigned int reset_counter1;
-       unsigned int reset_counter2;
-} reg;
-
-/* Compute all of the registers in preparation for enabling profiling.  */
-
-static void rm9000_reg_setup(struct op_counter_config *ctr)
-{
-       unsigned int control = 0;
-
-       /* Compute the performance counter control word.  */
-       /* For now count kernel and user mode */
-       if (ctr[0].enabled)
-               control |= RM9K_COUNTER1_EVENT(ctr[0].event) |
-                          RM9K_COUNTER1_KERNEL |
-                          RM9K_COUNTER1_USER |
-                          RM9K_COUNTER1_ENABLE;
-       if (ctr[1].enabled)
-               control |= RM9K_COUNTER2_EVENT(ctr[1].event) |
-                          RM9K_COUNTER2_KERNEL |
-                          RM9K_COUNTER2_USER |
-                          RM9K_COUNTER2_ENABLE;
-       reg.control = control;
-
-       reg.reset_counter1 = 0x80000000 - ctr[0].count;
-       reg.reset_counter2 = 0x80000000 - ctr[1].count;
-}
-
-/* Program all of the registers in preparation for enabling profiling.  */
-
-static void rm9000_cpu_setup(void *args)
-{
-       uint64_t perfcount;
-
-       perfcount = ((uint64_t) reg.reset_counter2 << 32) | reg.reset_counter1;
-       write_c0_perfcount(perfcount);
-}
-
-static void rm9000_cpu_start(void *args)
-{
-       /* Start all counters on current CPU */
-       write_c0_perfcontrol(reg.control);
-}
-
-static void rm9000_cpu_stop(void *args)
-{
-       /* Stop all counters on current CPU */
-       write_c0_perfcontrol(0);
-}
-
-static irqreturn_t rm9000_perfcount_handler(int irq, void *dev_id)
-{
-       unsigned int control = read_c0_perfcontrol();
-       struct pt_regs *regs = get_irq_regs();
-       uint32_t counter1, counter2;
-       uint64_t counters;
-
-       /*
-        * RM9000 combines two 32-bit performance counters into a single
-        * 64-bit coprocessor zero register.  To avoid a race updating the
-        * registers we need to stop the counters while we're messing with
-        * them ...
-        */
-       write_c0_perfcontrol(0);
-
-       counters = read_c0_perfcount();
-       counter1 = counters;
-       counter2 = counters >> 32;
-
-       if (control & RM9K_COUNTER1_OVERFLOW) {
-               oprofile_add_sample(regs, 0);
-               counter1 = reg.reset_counter1;
-       }
-       if (control & RM9K_COUNTER2_OVERFLOW) {
-               oprofile_add_sample(regs, 1);
-               counter2 = reg.reset_counter2;
-       }
-
-       counters = ((uint64_t)counter2 << 32) | counter1;
-       write_c0_perfcount(counters);
-       write_c0_perfcontrol(reg.control);
-
-       return IRQ_HANDLED;
-}
-
-static int __init rm9000_init(void)
-{
-       return request_irq(rm9000_perfcount_irq, rm9000_perfcount_handler,
-                          0, "Perfcounter", NULL);
-}
-
-static void rm9000_exit(void)
-{
-       free_irq(rm9000_perfcount_irq, NULL);
-}
-
-struct op_mips_model op_model_rm9000_ops = {
-       .reg_setup      = rm9000_reg_setup,
-       .cpu_setup      = rm9000_cpu_setup,
-       .init           = rm9000_init,
-       .exit           = rm9000_exit,
-       .cpu_start      = rm9000_cpu_start,
-       .cpu_stop       = rm9000_cpu_stop,
-       .cpu_type       = "mips/rm9000",
-       .num_counters   = 2
-};
index e13a71c..ce995d3 100644 (file)
@@ -34,8 +34,6 @@ obj-$(CONFIG_MIPS_MALTA)      += fixup-malta.o
 obj-$(CONFIG_PMC_MSP7120_GW)   += fixup-pmcmsp.o ops-pmcmsp.o
 obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
 obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o
-obj-$(CONFIG_PMC_YOSEMITE)     += fixup-yosemite.o ops-titan.o ops-titan-ht.o \
-                                  pci-yosemite.o
 obj-$(CONFIG_SGI_IP27)         += ops-bridge.o pci-ip27.o
 obj-$(CONFIG_SGI_IP32)         += fixup-ip32.o ops-mace.o pci-ip32.o
 obj-$(CONFIG_SIBYTE_SB1250)    += fixup-sb1250.o pci-sb1250.o
diff --git a/arch/mips/pci/fixup-yosemite.c b/arch/mips/pci/fixup-yosemite.c
deleted file mode 100644 (file)
index fdafb13..0000000
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2003 PMC-Sierra
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-       if (pin == 0)
-               return -1;
-
-       return 3;                       /* Everything goes to one irq bit */
-}
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
-       return 0;
-}
diff --git a/arch/mips/pci/ops-titan-ht.c b/arch/mips/pci/ops-titan-ht.c
deleted file mode 100644 (file)
index 57d54ad..0000000
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Copyright 2003 PMC-Sierra
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <asm/io.h>
-
-#include <asm/titan_dep.h>
-
-static int titan_ht_config_read_dword(struct pci_bus *bus, unsigned int devfn,
-       int offset, u32 *val)
-{
-       volatile uint32_t address;
-       int busno;
-
-       busno = bus->number;
-
-       address = (busno << 16) | (devfn << 8) | (offset & 0xfc) | 0x80000000;
-       if (busno != 0)
-               address |= 1;
-
-       /*
-        * RM9000 HT Errata: Issue back to back HT config
-        * transcations. Issue a BIU sync before and
-        * after the HT cycle
-        */
-
-       *(volatile int32_t *) 0xfb0000f0 |= 0x2;
-
-       udelay(30);
-
-       *(volatile int32_t *) 0xfb0006f8 = address;
-       *(val) = *(volatile int32_t *) 0xfb0006fc;
-
-       udelay(30);
-
-       * (volatile int32_t *) 0xfb0000f0 |= 0x2;
-
-       return PCIBIOS_SUCCESSFUL;
-}
-
-static int titan_ht_config_read(struct pci_bus *bus, unsigned int devfn,
-       int offset, int size, u32 *val)
-{
-       uint32_t dword;
-
-       titan_ht_config_read_dword(bus, devfn, offset, &dword);
-
-       dword >>= ((offset & 3) << 3);
-       dword &= (0xffffffffU >> ((4 - size) << 8));
-
-       return PCIBIOS_SUCCESSFUL;
-}
-
-static inline int titan_ht_config_write_dword(struct pci_bus *bus,
-       unsigned int devfn, int offset, u32 val)
-{
-       volatile uint32_t address;
-       int busno;
-
-       busno = bus->number;
-
-       address = (busno << 16) | (devfn << 8) | (offset & 0xfc) | 0x80000000;
-       if (busno != 0)
-               address |= 1;
-
-       *(volatile int32_t *) 0xfb0000f0 |= 0x2;
-
-       udelay(30);
-
-       *(volatile int32_t *) 0xfb0006f8 = address;
-       *(volatile int32_t *) 0xfb0006fc = val;
-
-       udelay(30);
-
-       *(volatile int32_t *) 0xfb0000f0 |= 0x2;
-
-       return PCIBIOS_SUCCESSFUL;
-}
-
-static int titan_ht_config_write(struct pci_bus *bus, unsigned int devfn,
-       int offset, int size, u32 val)
-{
-       uint32_t val1, val2, mask;
-
-       titan_ht_config_read_dword(bus, devfn, offset, &val2);
-
-       val1 = val << ((offset & 3) << 3);
-       mask = ~(0xffffffffU >> ((4 - size) << 8));
-       val2 &= ~(mask << ((offset & 3) << 8));
-
-       titan_ht_config_write_dword(bus, devfn, offset, val1 | val2);
-
-       return PCIBIOS_SUCCESSFUL;
-}
-
-struct pci_ops titan_ht_pci_ops = {
-       .read   = titan_ht_config_read,
-       .write  = titan_ht_config_write,
-};
diff --git a/arch/mips/pci/ops-titan.c b/arch/mips/pci/ops-titan.c
deleted file mode 100644 (file)
index ebf8fc4..0000000
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * Copyright 2003 PMC-Sierra
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- *  This program is free software; you can redistribute         it and/or modify it
- *  under  the terms of         the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED          ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,          INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED          TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA, OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN         CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-
-#include <asm/pci.h>
-#include <asm/io.h>
-#include <asm/rm9k-ocd.h>
-
-/*
- * PCI specific defines
- */
-#define        TITAN_PCI_0_CONFIG_ADDRESS      0x780
-#define        TITAN_PCI_0_CONFIG_DATA         0x784
-
-/*
- * Titan PCI Config Read Byte
- */
-static int titan_read_config(struct pci_bus *bus, unsigned int devfn, int reg,
-       int size, u32 * val)
-{
-       uint32_t address, tmp;
-       int dev, busno, func;
-
-       busno = bus->number;
-       dev = PCI_SLOT(devfn);
-       func = PCI_FUNC(devfn);
-
-       address = (busno << 16) | (dev << 11) | (func << 8) |
-                 (reg & 0xfc) | 0x80000000;
-
-
-       /* start the configuration cycle */
-       ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
-       tmp = ocd_readl(TITAN_PCI_0_CONFIG_DATA) >> ((reg & 3) << 3);
-
-       switch (size) {
-       case 1:
-               tmp &= 0xff;
-       case 2:
-               tmp &= 0xffff;
-       }
-       *val = tmp;
-
-       return PCIBIOS_SUCCESSFUL;
-}
-
-static int titan_write_config(struct pci_bus *bus, unsigned int devfn, int reg,
-       int size, u32 val)
-{
-       uint32_t address;
-       int dev, busno, func;
-
-       busno = bus->number;
-       dev = PCI_SLOT(devfn);
-       func = PCI_FUNC(devfn);
-
-       address = (busno << 16) | (dev << 11) | (func << 8) |
-               (reg & 0xfc) | 0x80000000;
-
-       /* start the configuration cycle */
-       ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
-
-       /* write the data */
-       switch (size) {
-       case 1:
-               ocd_writeb(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x3));
-               break;
-
-       case 2:
-               ocd_writew(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x2));
-               break;
-
-       case 4:
-               ocd_writel(val, TITAN_PCI_0_CONFIG_DATA);
-               break;
-       }
-
-       return PCIBIOS_SUCCESSFUL;
-}
-
-/*
- * Titan PCI structure
- */
-struct pci_ops titan_pci_ops = {
-       titan_read_config,
-       titan_write_config,
-};
diff --git a/arch/mips/pci/pci-yosemite.c b/arch/mips/pci/pci-yosemite.c
deleted file mode 100644 (file)
index cf5e1a2..0000000
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <asm/titan_dep.h>
-
-extern struct pci_ops titan_pci_ops;
-
-static struct resource py_mem_resource = {
-       .start  = 0xe0000000UL,
-       .end    = 0xe3ffffffUL,
-       .name   = "Titan PCI MEM",
-       .flags  = IORESOURCE_MEM
-};
-
-/*
- * PMON really reserves 16MB of I/O port space but that's stupid, nothing
- * needs that much since allocations are limited to 256 bytes per device
- * anyway.  So we just claim 64kB here.
- */
-#define TITAN_IO_SIZE  0x0000ffffUL
-#define TITAN_IO_BASE  0xe8000000UL
-
-static struct resource py_io_resource = {
-       .start  = 0x00001000UL,
-       .end    = TITAN_IO_SIZE - 1,
-       .name   = "Titan IO MEM",
-       .flags  = IORESOURCE_IO,
-};
-
-static struct pci_controller py_controller = {
-       .pci_ops        = &titan_pci_ops,
-       .mem_resource   = &py_mem_resource,
-       .mem_offset     = 0x00000000UL,
-       .io_resource    = &py_io_resource,
-       .io_offset      = 0x00000000UL
-};
-
-static char ioremap_failed[] __initdata = "Could not ioremap I/O port range";
-
-static int __init pmc_yosemite_setup(void)
-{
-       unsigned long io_v_base;
-
-       io_v_base = (unsigned long) ioremap(TITAN_IO_BASE, TITAN_IO_SIZE);
-       if (!io_v_base)
-               panic(ioremap_failed);
-
-       set_io_port_base(io_v_base);
-       py_controller.io_map_base = io_v_base;
-       TITAN_WRITE(RM9000x2_OCD_LKM7, TITAN_READ(RM9000x2_OCD_LKM7) | 1);
-
-       ioport_resource.end = TITAN_IO_SIZE - 1;
-
-       register_pci_controller(&py_controller);
-
-       return 0;
-}
-
-arch_initcall(pmc_yosemite_setup);
index bbd7608..3482b8c 100644 (file)
@@ -34,10 +34,6 @@ config PMC_MSP7120_FPGA
 
 endchoice
 
-config HYPERTRANSPORT
-       bool "Hypertransport Support for PMC-Sierra Yosemite"
-       depends on PMC_YOSEMITE
-
 config MSP_HAS_USB
        boolean
        depends on PMC_MSP
index f092f25..387fda6 100644 (file)
@@ -5,10 +5,3 @@ platform-$(CONFIG_PMC_MSP)     += pmc-sierra/msp71xx/
 cflags-$(CONFIG_PMC_MSP)       += -I$(srctree)/arch/mips/include/asm/pmc-sierra/msp71xx \
                                        -mno-branch-likely
 load-$(CONFIG_PMC_MSP)         += 0xffffffff80100000
-
-#
-# PMC-Sierra Yosemite
-#
-platform-$(CONFIG_PMC_YOSEMITE)        += pmc-sierra/yosemite/
-cflags-$(CONFIG_PMC_YOSEMITE)  += -I$(srctree)/arch/mips/include/asm/mach-yosemite
-load-$(CONFIG_PMC_YOSEMITE)    += 0xffffffff80100000
diff --git a/arch/mips/pmc-sierra/yosemite/Makefile b/arch/mips/pmc-sierra/yosemite/Makefile
deleted file mode 100644 (file)
index 5af95ec..0000000
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Makefile for the PMC-Sierra Titan
-#
-
-obj-y    += irq.o prom.o py-console.o setup.o
-
-obj-$(CONFIG_SMP)              += smp.o
diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
deleted file mode 100644 (file)
index d6f8bdf..0000000
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- *  Copyright (C) 2003 PMC-Sierra Inc.
- *  Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/*
- * Description:
- *
- * This code reads the ATMEL 24CXX EEPROM. The PMC-Sierra Yosemite board uses the ATMEL
- * 24C32/24C64 which uses two byte addressing as compared to 24C16. Note that this program
- * uses the serial port like /dev/ttyS0, to communicate with the EEPROM. Hence, you are
- * expected to have a connectivity from the EEPROM to the serial port. This program does
- * __not__ communicate using the I2C protocol
- */
-
-#include "atmel_read_eeprom.h"
-
-static void delay(int delay)
-{
-       while (delay--);
-}
-
-static void send_bit(unsigned char bit)
-{
-       scl_lo;
-       delay(TXX);
-       if (bit)
-               sda_hi;
-       else
-               sda_lo;
-
-       delay(TXX);
-       scl_hi;
-       delay(TXX);
-}
-
-static void send_ack(void)
-{
-       send_bit(0);
-}
-
-static void send_byte(unsigned char byte)
-{
-       int     i = 0;
-
-       for (i = 7; i >= 0; i--)
-               send_bit((byte >> i) & 0x01);
-}
-
-static void send_start(void)
-{
-       sda_hi;
-       delay(TXX);
-       scl_hi;
-       delay(TXX);
-       sda_lo;
-       delay(TXX);
-}
-
-static void send_stop(void)
-{
-       sda_lo;
-       delay(TXX);
-       scl_hi;
-       delay(TXX);
-       sda_hi;
-       delay(TXX);
-}
-
-static void do_idle(void)
-{
-       sda_hi;
-       scl_hi;
-       vcc_off;
-}
-
-static int recv_bit(void)
-{
-       int     status;
-
-       scl_lo;
-       delay(TXX);
-       sda_hi;
-       delay(TXX);
-       scl_hi;
-       delay(TXX);
-
-       return 1;
-}
-
-static unsigned char recv_byte(void) {
-        int i;
-        unsigned char byte=0;
-
-        for (i=7;i>=0;i--)
-                byte |= (recv_bit() << i);
-
-        return byte;
-}
-
-static int recv_ack(void)
-{
-       unsigned int    ack;
-
-       ack = (unsigned int)recv_bit();
-       scl_lo;
-
-       if (ack) {
-               do_idle();
-               printk(KERN_ERR "Error reading the Atmel 24C32/24C64 EEPROM\n");
-               return -1;
-       }
-
-       return ack;
-}
-
-/*
- * This function does the actual read of the EEPROM. It needs the buffer into which the
- * read data is copied, the size of the EEPROM being read and the buffer size
- */
-int read_eeprom(char *buffer, int eeprom_size, int size)
-{
-       int     i = 0, err;
-
-       send_start();
-       send_byte(W_HEADER);
-       recv_ack();
-
-       /* EEPROM with size of more than 2K need two byte addressing */
-       if (eeprom_size > 2048) {
-               send_byte(0x00);
-               recv_ack();
-       }
-
-       send_start();
-       send_byte(R_HEADER);
-       err = recv_ack();
-       if (err == -1)
-               return err;
-
-       for (i = 0; i < size; i++) {
-               *buffer++ = recv_byte();
-               send_ack();
-       }
-
-       /* Note : We should do some check if the buffer contains correct information */
-
-       send_stop();
-}
diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h
deleted file mode 100644 (file)
index d6c7ec4..0000000
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- *  arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
- *
- *  Copyright (C) 2003 PMC-Sierra Inc.
- *  Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *  Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/*
- * Header file for atmel_read_eeprom.c
- */
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <asm/pci.h>
-#include <asm/io.h>
-#include <linux/init.h>
-#include <asm/termios.h>
-#include <asm/ioctls.h>
-#include <linux/ioctl.h>
-#include <linux/fcntl.h>
-
-#define        DEFAULT_PORT    "/dev/ttyS0"    /* Port to open */
-#define        TXX             0               /* Dummy loop for spinning */
-
-#define        BLOCK_SEL       0x00
-#define        SLAVE_ADDR      0xa0
-#define        READ_BIT        0x01
-#define        WRITE_BIT       0x00
-#define        R_HEADER        SLAVE_ADDR + BLOCK_SEL + READ_BIT
-#define        W_HEADER        SLAVE_ADDR + BLOCK_SEL + WRITE_BIT
-
-/*
- * Clock, Voltages and Data
- */
-#define        vcc_off         (ioctl(fd, TIOCSBRK, 0))
-#define        vcc_on          (ioctl(fd, TIOCCBRK, 0))
-#define        sda_hi          (ioctl(fd, TIOCMBIS, &dtr))
-#define        sda_lo          (ioctl(fd, TIOCMBIC, &dtr))
-#define        scl_lo          (ioctl(fd, TIOCMBIC, &rts))
-#define        scl_hi          (ioctl(fd, TIOCMBIS, &rts))
-
-const char rts = TIOCM_RTS;
-const char dtr = TIOCM_DTR;
-int fd;
diff --git a/arch/mips/pmc-sierra/yosemite/ht-irq.c b/arch/mips/pmc-sierra/yosemite/ht-irq.c
deleted file mode 100644 (file)
index 62ead66..0000000
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2003 PMC-Sierra
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/pci.h>
-
-/*
- * HT Bus fixup for the Titan
- * XXX IRQ values need to change based on the board layout
- */
-void __init titan_ht_pcibios_fixup_bus(struct pci_bus *bus)
-{
-       /*
-        * PLX and SPKT related changes go here
-        */
-}
diff --git a/arch/mips/pmc-sierra/yosemite/ht.c b/arch/mips/pmc-sierra/yosemite/ht.c
deleted file mode 100644 (file)
index 14dc9c8..0000000
+++ /dev/null
@@ -1,404 +0,0 @@
-/*
- * Copyright 2003 PMC-Sierra
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <asm/pci.h>
-#include <asm/io.h>
-
-#include <linux/init.h>
-#include <asm/titan_dep.h>
-
-#ifdef CONFIG_HYPERTRANSPORT
-
-
-/*
- * This function check if the Hypertransport Link Initialization completed. If
- * it did, then proceed further with scanning bus #2
- */
-static __inline__ int check_titan_htlink(void)
-{
-        u32 val;
-
-        val = *(volatile uint32_t *)(RM9000x2_HTLINK_REG);
-        if (val & 0x00000020)
-                /* HT Link Initialization completed */
-                return 1;
-        else
-                return 0;
-}
-
-static int titan_ht_config_read_dword(struct pci_dev *device,
-                                             int offset, u32* val)
-{
-        int dev, bus, func;
-        uint32_t address_reg, data_reg;
-        uint32_t address;
-
-        bus = device->bus->number;
-        dev = PCI_SLOT(device->devfn);
-        func = PCI_FUNC(device->devfn);
-
-       /* XXX Need to change the Bus # */
-        if (bus > 2)
-                address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
-                                                        0x80000000 | 0x1;
-        else
-                address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
-
-        address_reg = RM9000x2_OCD_HTCFGA;
-        data_reg =  RM9000x2_OCD_HTCFGD;
-
-        RM9K_WRITE(address_reg, address);
-        RM9K_READ(data_reg, val);
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-
-static int titan_ht_config_read_word(struct pci_dev *device,
-                                             int offset, u16* val)
-{
-        int dev, bus, func;
-        uint32_t address_reg, data_reg;
-        uint32_t address;
-
-        bus = device->bus->number;
-        dev = PCI_SLOT(device->devfn);
-        func = PCI_FUNC(device->devfn);
-
-       /* XXX Need to change the Bus # */
-        if (bus > 2)
-                address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
-                                                0x80000000 | 0x1;
-        else
-                address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
-
-        address_reg = RM9000x2_OCD_HTCFGA;
-        data_reg =  RM9000x2_OCD_HTCFGD;
-
-        if ((offset & 0x3) == 0)
-                offset = 0x2;
-        else
-                offset = 0x0;
-
-        RM9K_WRITE(address_reg, address);
-        RM9K_READ_16(data_reg + offset, val);
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-
-u32 longswap(unsigned long l)
-{
-        unsigned char b1, b2, b3, b4;
-
-        b1 = l&255;
-        b2 = (l>>8)&255;
-        b3 = (l>>16)&255;
-        b4 = (l>>24)&255;
-
-        return ((b1<<24) + (b2<<16) + (b3<<8) + b4);
-}
-
-
-static int titan_ht_config_read_byte(struct pci_dev *device,
-                                             int offset, u8* val)
-{
-        int dev, bus, func;
-        uint32_t address_reg, data_reg;
-        uint32_t address;
-        int offset1;
-
-        bus = device->bus->number;
-        dev = PCI_SLOT(device->devfn);
-        func = PCI_FUNC(device->devfn);
-
-       /* XXX Need to change the Bus # */
-        if (bus > 2)
-                address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
-                                                        0x80000000 | 0x1;
-        else
-                address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
-
-        address_reg = RM9000x2_OCD_HTCFGA;
-        data_reg =  RM9000x2_OCD_HTCFGD;
-
-        RM9K_WRITE(address_reg, address);
-
-        if ((offset & 0x3) == 0) {
-                offset1 = 0x3;
-        }
-        if ((offset & 0x3) == 1) {
-                offset1 = 0x2;
-        }
-        if ((offset & 0x3) == 2) {
-                offset1 = 0x1;
-        }
-        if ((offset & 0x3) == 3) {
-                offset1 = 0x0;
-        }
-        RM9K_READ_8(data_reg + offset1, val);
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-
-static int titan_ht_config_write_dword(struct pci_dev *device,
-                                             int offset, u8 val)
-{
-        int dev, bus, func;
-        uint32_t address_reg, data_reg;
-        uint32_t address;
-
-        bus = device->bus->number;
-        dev = PCI_SLOT(device->devfn);
-        func = PCI_FUNC(device->devfn);
-
-       /* XXX Need to change the Bus # */
-        if (bus > 2)
-                address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
-                                                        0x80000000 | 0x1;
-        else
-              address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
-
-        address_reg = RM9000x2_OCD_HTCFGA;
-        data_reg =  RM9000x2_OCD_HTCFGD;
-
-        RM9K_WRITE(address_reg, address);
-        RM9K_WRITE(data_reg, val);
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-static int titan_ht_config_write_word(struct pci_dev *device,
-                                             int offset, u8 val)
-{
-        int dev, bus, func;
-        uint32_t address_reg, data_reg;
-        uint32_t address;
-
-        bus = device->bus->number;
-        dev = PCI_SLOT(device->devfn);
-        func = PCI_FUNC(device->devfn);
-
-       /* XXX Need to change the Bus # */
-        if (bus > 2)
-                address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
-                                0x80000000 | 0x1;
-        else
-                address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
-
-        address_reg = RM9000x2_OCD_HTCFGA;
-        data_reg =  RM9000x2_OCD_HTCFGD;
-
-        if ((offset & 0x3) == 0)
-                offset = 0x2;
-        else
-                offset = 0x0;
-
-        RM9K_WRITE(address_reg, address);
-        RM9K_WRITE_16(data_reg + offset, val);
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-static int titan_ht_config_write_byte(struct pci_dev *device,
-                                             int offset, u8 val)
-{
-        int dev, bus, func;
-        uint32_t address_reg, data_reg;
-        uint32_t address;
-        int offset1;
-
-        bus = device->bus->number;
-        dev = PCI_SLOT(device->devfn);
-        func = PCI_FUNC(device->devfn);
-
-       /* XXX Need to change the Bus # */
-        if (bus > 2)
-                address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
-                                0x80000000 | 0x1;
-        else
-                address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
-
-        address_reg = RM9000x2_OCD_HTCFGA;
-        data_reg =  RM9000x2_OCD_HTCFGD;
-
-        RM9K_WRITE(address_reg, address);
-
-        if ((offset & 0x3) == 0) {
-             offset1 = 0x3;
-        }
-        if ((offset & 0x3) == 1) {
-             offset1 = 0x2;
-        }
-        if ((offset & 0x3) == 2) {
-             offset1 = 0x1;
-        }
-        if ((offset & 0x3) == 3) {
-            offset1 = 0x0;
-        }
-
-        RM9K_WRITE_8(data_reg + offset1, val);
-        return PCIBIOS_SUCCESSFUL;
-}
-
-
-static void titan_pcibios_set_master(struct pci_dev *dev)
-{
-        u16 cmd;
-        int bus = dev->bus->number;
-
-       if (check_titan_htlink())
-            titan_ht_config_read_word(dev, PCI_COMMAND, &cmd);
-
-       cmd |= PCI_COMMAND_MASTER;
-
-       if (check_titan_htlink())
-            titan_ht_config_write_word(dev, PCI_COMMAND, cmd);
-}
-
-
-int pcibios_enable_resources(struct pci_dev *dev)
-{
-        u16 cmd, old_cmd;
-        u8 tmp1;
-        int idx;
-        struct resource *r;
-        int bus = dev->bus->number;
-
-       if (check_titan_htlink())
-            titan_ht_config_read_word(dev, PCI_COMMAND, &cmd);
-
-       old_cmd = cmd;
-        for (idx = 0; idx < 6; idx++) {
-                r = &dev->resource[idx];
-                if (!r->start && r->end) {
-                        printk(KERN_ERR
-                               "PCI: Device %s not available because of "
-                               "resource collisions\n", pci_name(dev));
-                        return -EINVAL;
-                }
-                if (r->flags & IORESOURCE_IO)
-                        cmd |= PCI_COMMAND_IO;
-                if (r->flags & IORESOURCE_MEM)
-                        cmd |= PCI_COMMAND_MEMORY;
-        }
-        if (cmd != old_cmd) {
-               if (check_titan_htlink())
-                   titan_ht_config_write_word(dev, PCI_COMMAND, cmd);
-       }
-
-       if (check_titan_htlink())
-               titan_ht_config_read_byte(dev, PCI_CACHE_LINE_SIZE, &tmp1);
-
-       if (tmp1 != 8) {
-                printk(KERN_WARNING "PCI setting cache line size to 8 from "
-                       "%d\n", tmp1);
-       }
-
-       if (check_titan_htlink())
-               titan_ht_config_write_byte(dev, PCI_CACHE_LINE_SIZE, 8);
-
-       if (check_titan_htlink())
-               titan_ht_config_read_byte(dev, PCI_LATENCY_TIMER, &tmp1);
-
-       if (tmp1 < 32 || tmp1 == 0xff) {
-                printk(KERN_WARNING "PCI setting latency timer to 32 from %d\n",
-                       tmp1);
-       }
-
-       if (check_titan_htlink())
-               titan_ht_config_write_byte(dev, PCI_LATENCY_TIMER, 32);
-
-       return 0;
-}
-
-
-int pcibios_enable_device(struct pci_dev *dev, int mask)
-{
-        return pcibios_enable_resources(dev);
-}
-
-resource_size_t pcibios_align_resource(void *data, const struct resource *res,
-                               resource_size_t size, resource_size_t align)
-{
-        struct pci_dev *dev = data;
-       resource_size_t start = res->start;
-
-        if (res->flags & IORESOURCE_IO) {
-                /* We need to avoid collisions with `mirrored' VGA ports
-                   and other strange ISA hardware, so we always want the
-                   addresses kilobyte aligned.  */
-                if (size > 0x100) {
-                        printk(KERN_ERR "PCI: I/O Region %s/%d too large"
-                               " (%ld bytes)\n", pci_name(dev),
-                                dev->resource - res, size);
-                }
-
-                start = (start + 1024 - 1) & ~(1024 - 1);
-        }
-
-       return start;
-}
-
-struct pci_ops titan_pci_ops = {
-        titan_ht_config_read_byte,
-        titan_ht_config_read_word,
-        titan_ht_config_read_dword,
-        titan_ht_config_write_byte,
-        titan_ht_config_write_word,
-        titan_ht_config_write_dword
-};
-
-void __init pcibios_fixup_bus(struct pci_bus *c)
-{
-        titan_ht_pcibios_fixup_bus(c);
-}
-
-void __init pcibios_init(void)
-{
-
-        /* Reset PCI I/O and PCI MEM values */
-       /* XXX Need to add the proper values here */
-        ioport_resource.start = 0xe0000000;
-        ioport_resource.end   = 0xe0000000 + 0x20000000 - 1;
-        iomem_resource.start  = 0xc0000000;
-        iomem_resource.end    = 0xc0000000 + 0x20000000 - 1;
-
-       /* XXX Need to add bus values */
-        pci_scan_bus(2, &titan_pci_ops, NULL);
-        pci_scan_bus(3, &titan_pci_ops, NULL);
-}
-
-unsigned __init int pcibios_assign_all_busses(void)
-{
-        /* We want to use the PCI bus detection done by PMON */
-        return 0;
-}
-
-#endif /* CONFIG_HYPERTRANSPORT */
diff --git a/arch/mips/pmc-sierra/yosemite/irq.c b/arch/mips/pmc-sierra/yosemite/irq.c
deleted file mode 100644 (file)
index 6590812..0000000
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * Copyright (C) 2003 PMC-Sierra Inc.
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Second level Interrupt handlers for the PMC-Sierra Titan/Yosemite board
- */
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/irq.h>
-#include <linux/timex.h>
-#include <linux/random.h>
-#include <linux/bitops.h>
-#include <asm/bootinfo.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/irq_cpu.h>
-#include <asm/mipsregs.h>
-#include <asm/titan_dep.h>
-
-/* Hypertransport specific */
-#define IRQ_ACK_BITS            0x00000000     /* Ack bits */
-
-#define HYPERTRANSPORT_INTA     0x78           /* INTA# */
-#define HYPERTRANSPORT_INTB     0x79           /* INTB# */
-#define HYPERTRANSPORT_INTC     0x7a           /* INTC# */
-#define HYPERTRANSPORT_INTD     0x7b           /* INTD# */
-
-extern void titan_mailbox_irq(void);
-
-#ifdef CONFIG_HYPERTRANSPORT
-/*
- * Handle hypertransport & SMP interrupts. The interrupt lines are scarce.
- * For interprocessor interrupts, the best thing to do is to use the INTMSG
- * register. We use the same external interrupt line, i.e. INTB3 and monitor
- * another status bit
- */
-static void ll_ht_smp_irq_handler(int irq)
-{
-       u32 status = OCD_READ(RM9000x2_OCD_INTP0STATUS4);
-
-       /* Ack all the bits that correspond to the interrupt sources */
-       if (status != 0)
-               OCD_WRITE(RM9000x2_OCD_INTP0STATUS4, IRQ_ACK_BITS);
-
-       status = OCD_READ(RM9000x2_OCD_INTP1STATUS4);
-       if (status != 0)
-               OCD_WRITE(RM9000x2_OCD_INTP1STATUS4, IRQ_ACK_BITS);
-
-#ifdef CONFIG_HT_LEVEL_TRIGGER
-       /*
-        * Level Trigger Mode only. Send the HT EOI message back to the source.
-        */
-       switch (status) {
-       case 0x1000000:
-               OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTA);
-               break;
-       case 0x2000000:
-               OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTB);
-               break;
-       case 0x4000000:
-               OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTC);
-               break;
-       case 0x8000000:
-               OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTD);
-               break;
-       case 0x0000001:
-               /* PLX */
-               OCD_WRITE(RM9000x2_OCD_HTEOI, 0x20);
-               OCD_WRITE(IRQ_CLEAR_REG, IRQ_ACK_BITS);
-               break;
-       case 0xf000000:
-               OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTA);
-               OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTB);
-               OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTC);
-               OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTD);
-               break;
-       }
-#endif /* CONFIG_HT_LEVEL_TRIGGER */
-
-       do_IRQ(irq);
-}
-#endif
-
-asmlinkage void plat_irq_dispatch(void)
-{
-       unsigned int cause = read_c0_cause();
-       unsigned int status = read_c0_status();
-       unsigned int pending = cause & status;
-
-       if (pending & STATUSF_IP7) {
-               do_IRQ(7);
-       } else if (pending & STATUSF_IP2) {
-#ifdef CONFIG_HYPERTRANSPORT
-               ll_ht_smp_irq_handler(2);
-#else
-               do_IRQ(2);
-#endif
-       } else if (pending & STATUSF_IP3) {
-               do_IRQ(3);
-       } else if (pending & STATUSF_IP4) {
-               do_IRQ(4);
-       } else if (pending & STATUSF_IP5) {
-#ifdef CONFIG_SMP
-               titan_mailbox_irq();
-#else
-               do_IRQ(5);
-#endif
-       } else if (pending & STATUSF_IP6) {
-               do_IRQ(4);
-       }
-}
-
-/*
- * Initialize the next level interrupt handler
- */
-void __init arch_init_irq(void)
-{
-       clear_c0_status(ST0_IM);
-
-       mips_cpu_irq_init();
-       rm7k_cpu_irq_init();
-       rm9k_cpu_irq_init();
-}
diff --git a/arch/mips/pmc-sierra/yosemite/prom.c b/arch/mips/pmc-sierra/yosemite/prom.c
deleted file mode 100644 (file)
index 6a2754c..0000000
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * Copyright (C) 2003, 2004 PMC-Sierra Inc.
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- * Copyright (C) 2004 Ralf Baechle
- */
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/pm.h>
-#include <linux/smp.h>
-
-#include <asm/io.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/reboot.h>
-#include <asm/smp-ops.h>
-#include <asm/bootinfo.h>
-#include <asm/pmon.h>
-
-#ifdef CONFIG_SMP
-extern void prom_grab_secondary(void);
-#else
-#define prom_grab_secondary() do { } while (0)
-#endif
-
-#include "setup.h"
-
-struct callvectors *debug_vectors;
-
-extern unsigned long yosemite_base;
-extern unsigned long cpu_clock_freq;
-
-const char *get_system_type(void)
-{
-       return "PMC-Sierra Yosemite";
-}
-
-static void prom_cpu0_exit(void *arg)
-{
-       void *nvram = (void *) YOSEMITE_RTC_BASE;
-
-       /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
-       writeb(0x84, nvram + 0xff7);
-
-       /* wait for the watchdog to go off */
-       mdelay(100 + (1000 / 16));
-
-       /* if the watchdog fails for some reason, let people know */
-       printk(KERN_NOTICE "Watchdog reset failed\n");
-}
-
-/*
- * Reset the NVRAM over the local bus
- */
-static void prom_exit(void)
-{
-#ifdef CONFIG_SMP
-       if (smp_processor_id())
-               /* CPU 1 */
-               smp_call_function(prom_cpu0_exit, NULL, 1);
-#endif
-       prom_cpu0_exit(NULL);
-}
-
-/*
- * Halt the system
- */
-static void prom_halt(void)
-{
-       printk(KERN_NOTICE "\n** You can safely turn off the power\n");
-       while (1)
-               __asm__(".set\tmips3\n\t" "wait\n\t" ".set\tmips0");
-}
-
-extern struct plat_smp_ops yos_smp_ops;
-
-/*
- * Init routine which accepts the variables from PMON
- */
-void __init prom_init(void)
-{
-       int argc = fw_arg0;
-       char **arg = (char **) fw_arg1;
-       char **env = (char **) fw_arg2;
-       struct callvectors *cv = (struct callvectors *) fw_arg3;
-       int i = 0;
-
-       /* Callbacks for halt, restart */
-       _machine_restart = (void (*)(char *)) prom_exit;
-       _machine_halt = prom_halt;
-       pm_power_off = prom_halt;
-
-       debug_vectors = cv;
-       arcs_cmdline[0] = '\0';
-
-       /* Get the boot parameters */
-       for (i = 1; i < argc; i++) {
-               if (strlen(arcs_cmdline) + strlen(arg[i]) + 1 >=
-                   sizeof(arcs_cmdline))
-                       break;
-
-               strcat(arcs_cmdline, arg[i]);
-               strcat(arcs_cmdline, " ");
-       }
-
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-       if ((strstr(arcs_cmdline, "console=ttyS")) == NULL)
-               strcat(arcs_cmdline, "console=ttyS0,115200");
-#endif
-
-       while (*env) {
-               if (strncmp("ocd_base", *env, strlen("ocd_base")) == 0)
-                       yosemite_base =
-                           simple_strtol(*env + strlen("ocd_base="), NULL,
-                                         16);
-
-               if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0)
-                       cpu_clock_freq =
-                           simple_strtol(*env + strlen("cpuclock="), NULL,
-                                         10);
-
-               env++;
-       }
-
-       prom_grab_secondary();
-
-       register_smp_ops(&yos_smp_ops);
-}
-
-void __init prom_free_prom_memory(void)
-{
-}
-
-void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
-{
-}
diff --git a/arch/mips/pmc-sierra/yosemite/py-console.c b/arch/mips/pmc-sierra/yosemite/py-console.c
deleted file mode 100644 (file)
index b7f1d9c..0000000
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001, 2002, 2004 Ralf Baechle
- */
-#include <linux/init.h>
-#include <linux/console.h>
-#include <linux/kdev_t.h>
-#include <linux/major.h>
-#include <linux/termios.h>
-#include <linux/sched.h>
-#include <linux/tty.h>
-
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <asm/serial.h>
-#include <asm/io.h>
-
-/* SUPERIO uart register map */
-struct yo_uartregs {
-       union {
-               volatile u8     rbr;    /* read only, DLAB == 0 */
-               volatile u8     thr;    /* write only, DLAB == 0 */
-               volatile u8     dll;    /* DLAB == 1 */
-       } u1;
-       union {
-               volatile u8     ier;    /* DLAB == 0 */
-               volatile u8     dlm;    /* DLAB == 1 */
-       } u2;
-       union {
-               volatile u8     iir;    /* read only */
-               volatile u8     fcr;    /* write only */
-       } u3;
-       volatile u8     iu_lcr;
-       volatile u8     iu_mcr;
-       volatile u8     iu_lsr;
-       volatile u8     iu_msr;
-       volatile u8     iu_scr;
-} yo_uregs_t;
-
-#define iu_rbr u1.rbr
-#define iu_thr u1.thr
-#define iu_dll u1.dll
-#define iu_ier u2.ier
-#define iu_dlm u2.dlm
-#define iu_iir u3.iir
-#define iu_fcr u3.fcr
-
-#define ssnop()                __asm__ __volatile__("sll       $0, $0, 1\n");
-#define ssnop_4()      do { ssnop(); ssnop(); ssnop(); ssnop(); } while (0)
-
-#define IO_BASE_64     0x9000000000000000ULL
-
-static unsigned char readb_outer_space(unsigned long long phys)
-{
-       unsigned long long vaddr = IO_BASE_64 | phys;
-       unsigned char res;
-       unsigned int sr;
-
-       sr = read_c0_status();
-       write_c0_status((sr | ST0_KX) & ~ ST0_IE);
-       ssnop_4();
-
-       __asm__ __volatile__ (
-       "       .set    mips3           \n"
-       "       ld      %0, %1          \n"
-       "       lbu     %0, (%0)        \n"
-       "       .set    mips0           \n"
-       : "=r" (res)
-       : "m" (vaddr));
-
-       write_c0_status(sr);
-       ssnop_4();
-
-       return res;
-}
-
-static void writeb_outer_space(unsigned long long phys, unsigned char c)
-{
-       unsigned long long vaddr = IO_BASE_64 | phys;
-       unsigned long tmp;
-       unsigned int sr;
-
-       sr = read_c0_status();
-       write_c0_status((sr | ST0_KX) & ~ ST0_IE);
-       ssnop_4();
-
-       __asm__ __volatile__ (
-       "       .set    mips3           \n"
-       "       ld      %0, %1          \n"
-       "       sb      %2, (%0)        \n"
-       "       .set    mips0           \n"
-       : "=&r" (tmp)
-       : "m" (vaddr), "r" (c));
-
-       write_c0_status(sr);
-       ssnop_4();
-}
-
-void prom_putchar(char c)
-{
-       unsigned long lsr = 0xfd000008ULL + offsetof(struct yo_uartregs, iu_lsr);
-       unsigned long thr = 0xfd000008ULL + offsetof(struct yo_uartregs, iu_thr);
-
-       while ((readb_outer_space(lsr) & 0x20) == 0);
-       writeb_outer_space(thr, c);
-}
diff --git a/arch/mips/pmc-sierra/yosemite/setup.c b/arch/mips/pmc-sierra/yosemite/setup.c
deleted file mode 100644 (file)
index b6472fc..0000000
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
- *  Copyright (C) 2003 PMC-Sierra Inc.
- *  Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/bcd.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/export.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/bootmem.h>
-#include <linux/swap.h>
-#include <linux/ioport.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/timex.h>
-#include <linux/termios.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-
-#include <asm/time.h>
-#include <asm/bootinfo.h>
-#include <asm/page.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/processor.h>
-#include <asm/reboot.h>
-#include <asm/serial.h>
-#include <asm/titan_dep.h>
-#include <asm/m48t37.h>
-
-#include "setup.h"
-
-unsigned char titan_ge_mac_addr_base[6] = {
-       // 0x00, 0x03, 0xcc, 0x1d, 0x22, 0x00
-       0x00, 0xe0, 0x04, 0x00, 0x00, 0x21
-};
-
-unsigned long cpu_clock_freq;
-unsigned long yosemite_base;
-
-static struct m48t37_rtc *m48t37_base;
-
-void __init bus_error_init(void)
-{
-       /* Do nothing */
-}
-
-
-void read_persistent_clock(struct timespec *ts)
-{
-       unsigned int year, month, day, hour, min, sec;
-       unsigned long flags;
-
-       spin_lock_irqsave(&rtc_lock, flags);
-       /* Stop the update to the time */
-       m48t37_base->control = 0x40;
-
-       year = bcd2bin(m48t37_base->year);
-       year += bcd2bin(m48t37_base->century) * 100;
-
-       month = bcd2bin(m48t37_base->month);
-       day = bcd2bin(m48t37_base->date);
-       hour = bcd2bin(m48t37_base->hour);
-       min = bcd2bin(m48t37_base->min);
-       sec = bcd2bin(m48t37_base->sec);
-
-       /* Start the update to the time again */
-       m48t37_base->control = 0x00;
-       spin_unlock_irqrestore(&rtc_lock, flags);
-
-       ts->tv_sec = mktime(year, month, day, hour, min, sec);
-       ts->tv_nsec = 0;
-}
-
-int rtc_mips_set_time(unsigned long tim)
-{
-       struct rtc_time tm;
-       unsigned long flags;
-
-       /*
-        * Convert to a more useful format -- note months count from 0
-        * and years from 1900
-        */
-       rtc_time_to_tm(tim, &tm);
-       tm.tm_year += 1900;
-       tm.tm_mon += 1;
-
-       spin_lock_irqsave(&rtc_lock, flags);
-       /* enable writing */
-       m48t37_base->control = 0x80;
-
-       /* year */
-       m48t37_base->year = bin2bcd(tm.tm_year % 100);
-       m48t37_base->century = bin2bcd(tm.tm_year / 100);
-
-       /* month */
-       m48t37_base->month = bin2bcd(tm.tm_mon);
-
-       /* day */
-       m48t37_base->date = bin2bcd(tm.tm_mday);
-
-       /* hour/min/sec */
-       m48t37_base->hour = bin2bcd(tm.tm_hour);
-       m48t37_base->min = bin2bcd(tm.tm_min);
-       m48t37_base->sec = bin2bcd(tm.tm_sec);
-
-       /* day of week -- not really used, but let's keep it up-to-date */
-       m48t37_base->day = bin2bcd(tm.tm_wday + 1);
-
-       /* disable writing */
-       m48t37_base->control = 0x00;
-       spin_unlock_irqrestore(&rtc_lock, flags);
-
-       return 0;
-}
-
-void __init plat_time_init(void)
-{
-       mips_hpt_frequency = cpu_clock_freq / 2;
-mips_hpt_frequency = 33000000 * 3 * 5;
-}
-
-unsigned long ocd_base;
-
-EXPORT_SYMBOL(ocd_base);
-
-/*
- * Common setup before any secondaries are started
- */
-
-#define TITAN_UART_CLK         3686400
-#define TITAN_SERIAL_BASE_BAUD (TITAN_UART_CLK / 16)
-#define TITAN_SERIAL_IRQ       4
-#define TITAN_SERIAL_BASE      0xfd000008UL
-
-static void __init py_map_ocd(void)
-{
-       ocd_base = (unsigned long) ioremap(OCD_BASE, OCD_SIZE);
-       if (!ocd_base)
-               panic("Mapping OCD failed - game over.  Your score is 0.");
-
-       /* Kludge for PMON bug ... */
-       OCD_WRITE(0x0710, 0x0ffff029);
-}
-
-static void __init py_uart_setup(void)
-{
-#ifdef CONFIG_SERIAL_8250
-       struct uart_port up;
-
-       /*
-        * Register to interrupt zero because we share the interrupt with
-        * the serial driver which we don't properly support yet.
-        */
-       memset(&up, 0, sizeof(up));
-       up.membase      = (unsigned char *) ioremap(TITAN_SERIAL_BASE, 8);
-       up.irq          = TITAN_SERIAL_IRQ;
-       up.uartclk      = TITAN_UART_CLK;
-       up.regshift     = 0;
-       up.iotype       = UPIO_MEM;
-       up.flags        = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
-       up.line         = 0;
-
-       if (early_serial_setup(&up))
-               printk(KERN_ERR "Early serial init of port 0 failed\n");
-#endif /* CONFIG_SERIAL_8250 */
-}
-
-static void __init py_rtc_setup(void)
-{
-       m48t37_base = ioremap(YOSEMITE_RTC_BASE, YOSEMITE_RTC_SIZE);
-       if (!m48t37_base)
-               printk(KERN_ERR "Mapping the RTC failed\n");
-}
-
-/* Not only time init but that's what the hook it's called through is named */
-static void __init py_late_time_init(void)
-{
-       py_map_ocd();
-       py_uart_setup();
-       py_rtc_setup();
-}
-
-void __init plat_mem_setup(void)
-{
-       late_time_init = py_late_time_init;
-
-       /* Add memory regions */
-       add_memory_region(0x00000000, 0x10000000, BOOT_MEM_RAM);
-
-#if 0 /* XXX Crash ...  */
-       OCD_WRITE(RM9000x2_OCD_HTSC,
-                 OCD_READ(RM9000x2_OCD_HTSC) | HYPERTRANSPORT_ENABLE);
-
-       /* Set the BAR. Shifted mode */
-       OCD_WRITE(RM9000x2_OCD_HTBAR0, HYPERTRANSPORT_BAR0_ADDR);
-       OCD_WRITE(RM9000x2_OCD_HTMASK0, HYPERTRANSPORT_SIZE0);
-#endif
-}
diff --git a/arch/mips/pmc-sierra/yosemite/setup.h b/arch/mips/pmc-sierra/yosemite/setup.h
deleted file mode 100644 (file)
index 1a01abf..0000000
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2003, 04 PMC-Sierra
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- * Copyright 2004 Ralf Baechle <ralf@linux-mips.org>
- *
- * Board specific definititions for the PMC-Sierra Yosemite
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#ifndef __SETUP_H__
-#define __SETUP_H__
-
-/* M48T37 RTC + NVRAM */
-#define        YOSEMITE_RTC_BASE               0xfc800000
-#define        YOSEMITE_RTC_SIZE               0x00800000
-
-#define HYPERTRANSPORT_BAR0_ADDR        0x00000006
-#define HYPERTRANSPORT_SIZE0            0x0fffffff
-#define HYPERTRANSPORT_BAR0_ATTR        0x00002000
-
-#define HYPERTRANSPORT_ENABLE           0x6
-
-/*
- * EEPROM Size
- */
-#define        TITAN_ATMEL_24C32_SIZE          32768
-#define        TITAN_ATMEL_24C64_SIZE          65536
-
-#endif /* __SETUP_H__ */
diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c
deleted file mode 100644 (file)
index 5edab2b..0000000
+++ /dev/null
@@ -1,185 +0,0 @@
-#include <linux/linkage.h>
-#include <linux/sched.h>
-#include <linux/smp.h>
-
-#include <asm/pmon.h>
-#include <asm/titan_dep.h>
-#include <asm/time.h>
-
-#define LAUNCHSTACK_SIZE 256
-
-static __cpuinitdata arch_spinlock_t launch_lock = __ARCH_SPIN_LOCK_UNLOCKED;
-
-static unsigned long secondary_sp __cpuinitdata;
-static unsigned long secondary_gp __cpuinitdata;
-
-static unsigned char launchstack[LAUNCHSTACK_SIZE] __initdata
-       __attribute__((aligned(2 * sizeof(long))));
-
-static void __init prom_smp_bootstrap(void)
-{
-       local_irq_disable();
-
-       while (arch_spin_is_locked(&launch_lock));
-
-       __asm__ __volatile__(
-       "       move    $sp, %0         \n"
-       "       move    $gp, %1         \n"
-       "       j       smp_bootstrap   \n"
-       :
-       : "r" (secondary_sp), "r" (secondary_gp));
-}
-
-/*
- * PMON is a fragile beast.  It'll blow up once the mappings it's littering
- * right into the middle of KSEG3 are blown away so we have to grab the slave
- * core early and keep it in a waiting loop.
- */
-void __init prom_grab_secondary(void)
-{
-       arch_spin_lock(&launch_lock);
-
-       pmon_cpustart(1, &prom_smp_bootstrap,
-                     launchstack + LAUNCHSTACK_SIZE, 0);
-}
-
-void titan_mailbox_irq(void)
-{
-       int cpu = smp_processor_id();
-       unsigned long status;
-
-       switch (cpu) {
-       case 0:
-               status = OCD_READ(RM9000x2_OCD_INTP0STATUS3);
-               OCD_WRITE(RM9000x2_OCD_INTP0CLEAR3, status);
-
-               if (status & 0x2)
-                       smp_call_function_interrupt();
-               if (status & 0x4)
-                       scheduler_ipi();
-               break;
-
-       case 1:
-               status = OCD_READ(RM9000x2_OCD_INTP1STATUS3);
-               OCD_WRITE(RM9000x2_OCD_INTP1CLEAR3, status);
-
-               if (status & 0x2)
-                       smp_call_function_interrupt();
-               if (status & 0x4)
-                       scheduler_ipi();
-               break;
-       }
-}
-
-/*
- * Send inter-processor interrupt
- */
-static void yos_send_ipi_single(int cpu, unsigned int action)
-{
-       /*
-        * Generate an INTMSG so that it can be sent over to the
-        * destination CPU. The INTMSG will put the STATUS bits
-        * based on the action desired. An alternative strategy
-        * is to write to the Interrupt Set register, read the
-        * Interrupt Status register and clear the Interrupt
-        * Clear register. The latter is preffered.
-        */
-       switch (action) {
-       case SMP_RESCHEDULE_YOURSELF:
-               if (cpu == 1)
-                       OCD_WRITE(RM9000x2_OCD_INTP1SET3, 4);
-               else
-                       OCD_WRITE(RM9000x2_OCD_INTP0SET3, 4);
-               break;
-
-       case SMP_CALL_FUNCTION:
-               if (cpu == 1)
-                       OCD_WRITE(RM9000x2_OCD_INTP1SET3, 2);
-               else
-                       OCD_WRITE(RM9000x2_OCD_INTP0SET3, 2);
-               break;
-       }
-}
-
-static void yos_send_ipi_mask(const struct cpumask *mask, unsigned int action)
-{
-       unsigned int i;
-
-       for_each_cpu(i, mask)
-               yos_send_ipi_single(i, action);
-}
-
-/*
- *  After we've done initial boot, this function is called to allow the
- *  board code to clean up state, if needed
- */
-static void __cpuinit yos_init_secondary(void)
-{
-}
-
-static void __cpuinit yos_smp_finish(void)
-{
-       set_c0_status(ST0_CO | ST0_IM | ST0_IE);
-}
-
-/* Hook for after all CPUs are online */
-static void yos_cpus_done(void)
-{
-}
-
-/*
- * Firmware CPU startup hook
- * Complicated by PMON's weird interface which tries to minimic the UNIX fork.
- * It launches the next * available CPU and copies some information on the
- * stack so the first thing we do is throw away that stuff and load useful
- * values into the registers ...
- */
-static void __cpuinit yos_boot_secondary(int cpu, struct task_struct *idle)
-{
-       unsigned long gp = (unsigned long) task_thread_info(idle);
-       unsigned long sp = __KSTK_TOS(idle);
-
-       secondary_sp = sp;
-       secondary_gp = gp;
-
-       arch_spin_unlock(&launch_lock);
-}
-
-/*
- * Detect available CPUs, populate cpu_possible_mask before smp_init
- *
- * We don't want to start the secondary CPU yet nor do we have a nice probing
- * feature in PMON so we just assume presence of the secondary core.
- */
-static void __init yos_smp_setup(void)
-{
-       int i;
-
-       init_cpu_possible(cpu_none_mask);
-
-       for (i = 0; i < 2; i++) {
-               set_cpu_possible(i, true);
-               __cpu_number_map[i]     = i;
-               __cpu_logical_map[i]    = i;
-       }
-}
-
-static void __init yos_prepare_cpus(unsigned int max_cpus)
-{
-       /*
-        * Be paranoid.  Enable the IPI only if we're really about to go SMP.
-        */
-       if (num_possible_cpus())
-               set_c0_status(STATUSF_IP5);
-}
-
-struct plat_smp_ops yos_smp_ops = {
-       .send_ipi_single        = yos_send_ipi_single,
-       .send_ipi_mask          = yos_send_ipi_mask,
-       .init_secondary         = yos_init_secondary,
-       .smp_finish             = yos_smp_finish,
-       .cpus_done              = yos_cpus_done,
-       .boot_secondary         = yos_boot_secondary,
-       .smp_setup              = yos_smp_setup,
-       .prepare_cpus           = yos_prepare_cpus,
-};