radeon/llvm: Fix CCReg definitions on SI

diff --git a/src/gallium/drivers/radeon/SIGenRegisterInfo.pl b/src/gallium/drivers/radeon/SIGenRegisterInfo.pl
index 68b4fe3..110c04f 100644 (file)
--- a/src/gallium/drivers/radeon/SIGenRegisterInfo.pl
+++ b/src/gallium/drivers/radeon/SIGenRegisterInfo.pl
@@ -167,7 +167,8 @@ def AllReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
     (add VReg_32, SReg_32)
 >;
 
-def CCReg : RegisterClass<"AMDGPU", [f32], 32, (add VCC, SCC)>;
+def SCCReg : RegisterClass<"AMDGPU", [i1], 1, (add SCC)>;
+def VCCReg : RegisterClass<"AMDGPU", [i1], 1, (add VCC)>;
 
 STRING
 
@@ -264,6 +265,12 @@ sub print_reg_class {
     print "def $reg_name : $reg_prefix\_$reg_width <$i, \"$reg_name\", [ ", join(',', @sub_regs) , "]>;\n";
     push (@registers, $reg_name);
   }
+
+  #Add VCC to SReg_64
+  if ($class_prefix eq 'SReg' and $reg_width == 64) {
+    push (@registers, 'VCC')
+  }
+
   my $reg_list = join(', ', @registers);
 
   print "def $class_prefix\_$reg_width : RegisterClass<\"AMDGPU\", [" . join (', ', @types) . "], $reg_width,\n  (add $reg_list)\n>{\n";

diff --git a/src/gallium/drivers/radeon/SIInstrFormats.td b/src/gallium/drivers/radeon/SIInstrFormats.td
index ac8465c..79f4708 100644 (file)
--- a/src/gallium/drivers/radeon/SIInstrFormats.td
+++ b/src/gallium/drivers/radeon/SIInstrFormats.td
@@ -121,8 +121,8 @@ multiclass VOPC_64 <bits<8> op, string opName, list<dag> pattern> {
 }
 
 class SOPC_32 <bits<7> op, string opName, list<dag> pattern>
-  : SOPC <op, (outs CCReg:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>;
+  : SOPC <op, (outs SCCReg:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>;
 
 class SOPC_64 <bits<7> op, string opName, list<dag> pattern>
-  : SOPC <op, (outs CCReg:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
+  : SOPC <op, (outs SCCReg:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;