[MIPS/GAS] Split Loongson EXT Instructions from loongson3a.

bfd/
	 * elfxx-mips.c (infer_mips_abiflags): Use ases instead of
	 isa_ext for infer ABI flags.
	 (print_mips_ases): Add Loongson EXT extension.

binutils/
	 * readelf.c (print_mips_ases): Add Loongson EXT extension.

elfcpp/
	 * mips.h (AFL_ASE_LOONGSON_EXT): New enum.

gas/
	 * NEWS: Mention Loongson EXTensions (EXT) support.
	 * config/tc-mips.c (options): Add OPTION_LOONGSON_EXT and
	 OPTION_NO_LOONGSON_EXT.
	 (md_longopts): Likewise.
	 (mips_ases): Define availability for EXT.
	 (mips_convert_ase_flags): Map ASE_LOONGSON_EXT to
	 AFL_ASE_LOONGSON_EXT.
	 (mips_cpu_info_table): Add ASE_LOONGSON_EXT for loongson3a.
	 (md_show_usage): Add help for -mloongson-ext and
	 -mno-loongson-ext.
	 * doc/as.texi: Document -mloongson-ext, -mno-loongson-ext.
	 * doc/c-mips.texi: Document -mloongson-ext, -mno-loongson-ext,
	 .set loongson-ext and .set noloongson-ext.
	 * testsuite/gas/mips/loongson-mmi.d: Add ASE flag.

include/
	 * elf/mips.h (AFL_ASE_LOONGSON_EXT): New macro.
	 (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT.
	 * opcode/mips.h (ASE_LOONGSON_EXT): New macro.

opcodes/
	 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
	 descriptors.
	 (parse_mips_ase_option): Handle -M loongson-ext option.
	 (print_mips_disassembler_options): Document -M loongson-ext.
	 * mips-opc.c (IL3A): Delete.
	 * mips-opc.c (LEXT): New macro.
	 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
	 instructions.

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 0f292a5..bf32a61 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,5 +1,11 @@
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
+        * elfxx-mips.c (infer_mips_abiflags): Use ases instead of
+        isa_ext for infer ABI flags.
+        (print_mips_ases): Add Loongson EXT extension.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
        * elfxx-mips.c (print_mips_ases): Add CAM extension.
 
 2018-08-27  H.J. Lu  <hongjiu.lu@intel.com>

diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 80cc8c0..e4275d7 100644 (file)
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -14250,7 +14250,7 @@ infer_mips_abiflags (bfd *abfd, Elf_Internal_ABIFlags_v0* abiflags)
       && abiflags->fp_abi != Val_GNU_MIPS_ABI_FP_SOFT
       && abiflags->fp_abi != Val_GNU_MIPS_ABI_FP_64A
       && abiflags->isa_level >= 32
-      && abiflags->isa_ext != AFL_EXT_LOONGSON_3A)
+      && abiflags->ases != AFL_ASE_LOONGSON_EXT)
     abiflags->flags1 |= AFL_FLAGS1_ODDSPREG;
 }
 
@@ -15679,6 +15679,8 @@ print_mips_ases (FILE *file, unsigned int mask)
     fputs ("\n\tLoongson MMI ASE", file);
   if (mask & AFL_ASE_LOONGSON_CAM)
     fputs ("\n\tLoongson CAM ASE", file);
+  if (mask & AFL_ASE_LOONGSON_EXT)
+    fputs ("\n\tLoongson EXT ASE", file);
   if (mask == 0)
     fprintf (file, "\n\t%s", _("None"));
   else if ((mask & ~AFL_ASE_MASK) != 0)

diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 1bd5cf6..20e9ad0 100644 (file)
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,5 +1,9 @@
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
+        * readelf.c (print_mips_ases): Add Loongson EXT extension.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
        * readelf.c (print_mips_ases): Add CAM extension.
 
 2018-08-27  H.J. Lu  <hongjiu.lu@intel.com>

diff --git a/binutils/readelf.c b/binutils/readelf.c
index 039717a..92353c5 100644 (file)
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -15653,6 +15653,8 @@ print_mips_ases (unsigned int mask)
     fputs ("\n\tLoongson MMI ASE", stdout);
   if (mask & AFL_ASE_LOONGSON_CAM)
     fputs ("\n\tLoongson CAM ASE", stdout);
+  if (mask & AFL_ASE_LOONGSON_EXT)
+    fputs ("\n\tLoongson EXT ASE", stdout);
   if (mask == 0)
     fprintf (stdout, "\n\t%s", _("None"));
   else if ((mask & ~AFL_ASE_MASK) != 0)

diff --git a/elfcpp/ChangeLog b/elfcpp/ChangeLog
index fa33bf1..075f247 100644 (file)
--- a/elfcpp/ChangeLog
+++ b/elfcpp/ChangeLog
@@ -1,3 +1,7 @@
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+        * mips.h (AFL_ASE_LOONGSON_EXT): New enum.
+
 2018-07-06  Alan Modra  <amodra@gmail.com>
 
        * powerpc.h (Tag_GNU_Power_ABI_FP): Define.

diff --git a/elfcpp/mips.h b/elfcpp/mips.h
index cac8592..5a59599 100644 (file)
--- a/elfcpp/mips.h
+++ b/elfcpp/mips.h
@@ -308,7 +308,9 @@ enum
   // MICROMIPS ASE.
   AFL_ASE_MICROMIPS = 0x00000800,
   // XPA ASE.
-  AFL_ASE_XPA = 0x00001000
+  AFL_ASE_XPA = 0x00001000,
+  // Loongson EXT ASE.
+  AFL_ASE_LOONGSON_EXT = 0x00002000
 };
 
 // Values for the isa_ext word of an ABI flags structure.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 30b82ae..94fd28c 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,22 @@
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
+        * NEWS: Mention Loongson EXTensions (EXT) support.
+        * config/tc-mips.c (options): Add OPTION_LOONGSON_EXT and
+        OPTION_NO_LOONGSON_EXT.
+        (md_longopts): Likewise.
+        (mips_ases): Define availability for EXT.
+        (mips_convert_ase_flags): Map ASE_LOONGSON_EXT to
+        AFL_ASE_LOONGSON_EXT.
+        (mips_cpu_info_table): Add ASE_LOONGSON_EXT for loongson3a.
+        (md_show_usage): Add help for -mloongson-ext and
+        -mno-loongson-ext.
+        * doc/as.texi: Document -mloongson-ext, -mno-loongson-ext.
+        * doc/c-mips.texi: Document -mloongson-ext, -mno-loongson-ext,
+        .set loongson-ext and .set noloongson-ext.
+        * testsuite/gas/mips/loongson-mmi.d: Add ASE flag.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
        * NEWS: Mention Loongson Content Address Memory (CAM)
        support.
        * config/tc-mips.c (options): Add OPTION_LOONGSON_CAM and

diff --git a/gas/NEWS b/gas/NEWS
index b710c7a..48854e5 100644 (file)
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Add support for the MIPS Loongson EXTensions (EXT) instructions.
+
 * Add support for the MIPS Loongson Content Address Memory (CAM) ASE.
 
 * Add support for the C-SKY processor series.

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 1f58a6d..51eee00 100644 (file)
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -1533,6 +1533,8 @@ enum options
     OPTION_NO_LOONGSON_MMI,
     OPTION_LOONGSON_CAM,
     OPTION_NO_LOONGSON_CAM,
+    OPTION_LOONGSON_EXT,
+    OPTION_NO_LOONGSON_EXT,
     OPTION_END_OF_ENUM
   };
 
@@ -1597,6 +1599,8 @@ struct option md_longopts[] =
   {"mno-loongson-mmi", no_argument, NULL, OPTION_NO_LOONGSON_MMI},
   {"mloongson-cam", no_argument, NULL, OPTION_LOONGSON_CAM},
   {"mno-loongson-cam", no_argument, NULL, OPTION_NO_LOONGSON_CAM},
+  {"mloongson-ext", no_argument, NULL, OPTION_LOONGSON_EXT},
+  {"mno-loongson-ext", no_argument, NULL, OPTION_NO_LOONGSON_EXT},
 
   /* Old-style architecture options.  Don't add more of these.  */
   {"m4650", no_argument, NULL, OPTION_M4650},
@@ -1804,6 +1808,11 @@ static const struct mips_ase mips_ases[] = {
     OPTION_LOONGSON_CAM, OPTION_NO_LOONGSON_CAM,
     0, 0, -1, -1,
     -1 },
+
+  { "loongson-ext", ASE_LOONGSON_EXT, 0,
+    OPTION_LOONGSON_EXT, OPTION_NO_LOONGSON_EXT,
+    0, 0, -1, -1,
+    -1 },
 };
 
 /* The set of ASEs that require -mfp64.  */
@@ -19039,6 +19048,8 @@ mips_convert_ase_flags (int ase)
     ext_ases |= AFL_ASE_LOONGSON_MMI;
   if (ase & ASE_LOONGSON_CAM)
     ext_ases |= AFL_ASE_LOONGSON_CAM;
+  if (ase & ASE_LOONGSON_EXT)
+    ext_ases |= AFL_ASE_LOONGSON_EXT;
 
   return ext_ases;
 }
@@ -19786,8 +19797,8 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
 
   /* MIPS 64 Release 2 */
   /* Loongson CPU core */
-  { "loongson3a",     0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM,  ISA_MIPS64R2,
-     CPU_LOONGSON_3A },
+  { "loongson3a",     0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT,
+     ISA_MIPS64R2,     CPU_LOONGSON_3A },
 
   /* Cavium Networks Octeon CPU core */
   { "octeon",        0, 0,                     ISA_MIPS64R2, CPU_OCTEON },
@@ -20066,6 +20077,9 @@ MIPS options:\n\
 -mloongson-cam         generate Loongson Content Address Memory (CAM) instructions\n\
 -mno-loongson-cam      do not generate Loongson Content Address Memory Instructions\n"));
   fprintf (stream, _("\
+-mloongson-ext         generate Loongson EXTensions (EXT) instructions\n\
+-mno-loongson-ext      do not generate Loongson EXTensions Instructions\n"));
+  fprintf (stream, _("\
 -minsn32               only generate 32-bit microMIPS instructions\n\
 -mno-insn32            generate all microMIPS instructions\n"));
   fprintf (stream, _("\

diff --git a/gas/doc/as.texi b/gas/doc/as.texi
index 5d10e07..92dd366 100644 (file)
--- a/gas/doc/as.texi
+++ b/gas/doc/as.texi
@@ -446,6 +446,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-mginv}] [@b{-mno-ginv}]
    [@b{-mloongson-mmi}] [@b{-mno-loongson-mmi}]
    [@b{-mloongson-cam}] [@b{-mno-loongson-cam}]
+   [@b{-mloongson-ext}] [@b{-mno-loongson-ext}]
    [@b{-minsn32}] [@b{-mno-insn32}]
    [@b{-mfix7000}] [@b{-mno-fix7000}]
    [@b{-mfix-rm7000}] [@b{-mno-fix-rm7000}]
@@ -1580,6 +1581,12 @@ Generate code for the Loongson Content Address Memory (CAM) instructions.
 This tells the assembler to accept Loongson CAM instructions.
 @samp{-mno-loongson-cam} turns off this option.
 
+@item -mloongson-ext
+@itemx -mno-loongson-ext
+Generate code for the Loongson EXTensions (EXT) instructions.
+This tells the assembler to accept Loongson EXT instructions.
+@samp{-mno-loongson-ext} turns off this option.
+
 @item -minsn32
 @itemx -mno-insn32
 Only use 32-bit instruction encodings when generating code for the

diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 7d5d869..80b4160 100644 (file)
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -260,6 +260,13 @@ Application Specific Extension.  This tells the assembler to accept CAM
 instructions.
 @samp{-mno-loongson-cam} turns off this option.
 
+@item -mloongson-ext
+@itemx -mno-loongson-ext
+Generate code for the Loongson EXTensions (EXT) instructions
+Application Specific Extension.  This tells the assembler to accept EXT
+instructions.
+@samp{-mno-loongson-ext} turns off this option.
+
 @item -minsn32
 @itemx -mno-insn32
 Only use 32-bit instruction encodings when generating code for the
@@ -1167,6 +1174,14 @@ instructions from the Loongson CAM from that point on in the assembly.
 The @code{.set noloongson-cam} directive prevents Loongson CAM instructions
 from being accepted.
 
+@cindex Loongson EXTensions (EXT) instructions generation override
+@kindex @code{.set loongson-ext}
+@kindex @code{.set noloongson-ext}
+The directive @code{.set loongson-ext} makes the assembler accept
+instructions from the Loongson EXT from that point on in the assembly.
+The @code{.set noloongson-ext} directive prevents Loongson EXT instructions
+from being accepted.
+
 Traditional MIPS assemblers do not support these directives.
 
 @node MIPS Floating-Point

diff --git a/gas/testsuite/gas/mips/loongson-3a-mmi.d b/gas/testsuite/gas/mips/loongson-3a-mmi.d
index 81503cb..8319a7d 100644 (file)
--- a/gas/testsuite/gas/mips/loongson-3a-mmi.d
+++ b/gas/testsuite/gas/mips/loongson-3a-mmi.d
@@ -16,6 +16,7 @@ ISA Extension: Loongson 3A
 ASEs:
        Loongson MMI ASE
        Loongson CAM ASE
+       Loongson EXT ASE
 FLAGS 1: .*
 FLAGS 2: .*
 

diff --git a/include/ChangeLog b/include/ChangeLog
index 27f0202..b45a328 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,11 @@
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
+        * elf/mips.h (AFL_ASE_LOONGSON_EXT): New macro.
+        (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT.
+        * opcode/mips.h (ASE_LOONGSON_EXT): New macro.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
        * elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro.
        (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_CAM.
        * opcode/mips.h (ASE_LOONGSON_CAM): New macro.

diff --git a/include/elf/mips.h b/include/elf/mips.h
index f76f14f..cd76139 100644 (file)
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -1240,7 +1240,8 @@ extern void bfd_mips_elf_swap_abiflags_v0_out
 #define AFL_ASE_GINV         0x00020000 /* GINV ASE.  */
 #define AFL_ASE_LOONGSON_MMI 0x00040000 /* Loongson MMI ASE.  */
 #define AFL_ASE_LOONGSON_CAM 0x00080000 /* Loongson CAM ASE.  */
-#define AFL_ASE_MASK         0x000effff /* All ASEs.  */
+#define AFL_ASE_LOONGSON_EXT 0x00100000 /* Loongson EXT instructions.  */
+#define AFL_ASE_MASK         0x001effff /* All ASEs.  */
 
 /* Values for the isa_ext word of an ABI flags structure.  */
 

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index abcb47d..4d60cbc 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1306,6 +1306,8 @@ static const unsigned int mips_isa_table[] = {
 #define ASE_LOONGSON_MMI       0x00200000
 /* Loongson Content Address Memory (CAM).  */
 #define ASE_LOONGSON_CAM       0x00400000
+/* Loongson EXTensions (EXT) instructions.  */
+#define ASE_LOONGSON_EXT       0x00800000
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ce6624c..13a1e15 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,16 @@
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
+        * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
+        descriptors.
+        (parse_mips_ase_option): Handle -M loongson-ext option.
+        (print_mips_disassembler_options): Document -M loongson-ext.
+        * mips-opc.c (IL3A): Delete.
+        * mips-opc.c (LEXT): New macro.
+        (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
+        instructions.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
        * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
        descriptors.
        (parse_mips_ase_option): Handle -M loongson-cam option.

diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 832d4dc..277d79d 100644 (file)
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -630,7 +630,7 @@ const struct mips_arch_choice mips_arch_choices[] =
     NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
 
   { "loongson3a",   1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
-    ISA_MIPS64R2 | INSN_LOONGSON_3A, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM,
+    ISA_MIPS64R2, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT,
     mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264,
     mips_hwr_names_numeric },
 
@@ -948,6 +948,12 @@ parse_mips_ase_option (const char *option)
       return TRUE;
     }
 
+  if (CONST_STRNEQ (option, "loongson-ext"))
+    {
+      mips_ase |= ASE_LOONGSON_EXT;
+      return TRUE;
+    }
+
   return FALSE;
 }
 
@@ -2603,6 +2609,10 @@ static struct
                  N_("Recognize the Loongson Content Address Memory (CAM) "
                     " instructions.\n"),
                  MIPS_OPTION_ARG_NONE },
+  { "loongson-ext",
+                 N_("Recognize the Loongson EXTensions (EXT) "
+                    " instructions.\n"),
+                 MIPS_OPTION_ARG_NONE },
   { "gpr-names=", N_("Print GPR names according to specified ABI.\n\
                   Default: based on binary being disassembled.\n"),
                  MIPS_OPTION_ARG_ABI },

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 5c9f28a..5e4690d 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -308,7 +308,6 @@ decode_mips_operand (const char *p)
 
 #define IL2E    (INSN_LOONGSON_2E)
 #define IL2F    (INSN_LOONGSON_2F)
-#define IL3A    (INSN_LOONGSON_3A)
 
 #define P3     INSN_4650
 #define L1     INSN_4010
@@ -418,6 +417,9 @@ decode_mips_operand (const char *p)
 /* Loongson Content Address Memory (CAM) support.  */
 #define LCAM   ASE_LOONGSON_CAM
 
+/* Loongson EXTensions (EXT) instructions support.  */
+#define LEXT   ASE_LOONGSON_EXT
+
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
    for arguments must apear in the correct order in this table for the
@@ -466,56 +468,56 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"campv",              "d,s",          0x70000035, 0xfc1f07ff, WR_1|RD_2,              0,              0,              LCAM,   0 },
 {"camwi",              "d,s,t",        0x700000b5, 0xfc0007ff, RD_1|RD_2|RD_3,         0,              0,              LCAM,   0 },
 {"ramri",              "d,s",          0x700000f5, 0xfc1f07ff, WR_1|RD_2,              0,              0,              LCAM,   0 },
-{"gsle",               "s,t",          0x70000026, 0xfc00ffff, RD_1|RD_2,              0,              IL3A,           0,      0 },
-{"gsgt",               "s,t",          0x70000027, 0xfc00ffff, RD_1|RD_2,              0,              IL3A,           0,      0 },
-{"gslble",             "t,b,d",        0xc8000010, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gslbgt",             "t,b,d",        0xc8000011, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gslhle",             "t,b,d",        0xc8000012, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gslhgt",             "t,b,d",        0xc8000013, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gslwle",             "t,b,d",        0xc8000014, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gslwgt",             "t,b,d",        0xc8000015, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gsldle",             "t,b,d",        0xc8000016, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gsldgt",             "t,b,d",        0xc8000017, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gssble",             "t,b,d",        0xe8000010, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gssbgt",             "t,b,d",        0xe8000011, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gsshle",             "t,b,d",        0xe8000012, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gsshgt",             "t,b,d",        0xe8000013, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gsswle",             "t,b,d",        0xe8000014, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gsswgt",             "t,b,d",        0xe8000015, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gssdle",             "t,b,d",        0xe8000016, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gssdgt",             "t,b,d",        0xe8000017, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gslwlec1",           "T,b,d",        0xc8000018, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gslwgtc1",           "T,b,d",        0xc8000019, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gsldlec1",           "T,b,d",        0xc800001a, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gsldgtc1",           "T,b,d",        0xc800001b, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
-{"gsswlec1",           "T,b,d",        0xe800001c, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gsswgtc1",           "T,b,d",        0xe800001d, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gssdlec1",           "T,b,d",        0xe800001e, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gssdgtc1",           "T,b,d",        0xe800001f, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gslwlc1",            "T,+a(b)",      0xc8000004, 0xfc00c03f, WR_1|RD_3|LM,           0,              IL3A,           0,      0 },
-{"gslwrc1",            "T,+a(b)",      0xc8000005, 0xfc00c03f, WR_1|RD_3|LM,           0,              IL3A,           0,      0 },
-{"gsldlc1",            "T,+a(b)",      0xc8000006, 0xfc00c03f, WR_1|RD_3|LM,           0,              IL3A,           0,      0 },
-{"gsldrc1",            "T,+a(b)",      0xc8000007, 0xfc00c03f, WR_1|RD_3|LM,           0,              IL3A,           0,      0 },
-{"gsswlc1",            "T,+a(b)",      0xe8000004, 0xfc00c03f, RD_1|RD_3|SM,           0,              IL3A,           0,      0 },
-{"gsswrc1",            "T,+a(b)",      0xe8000005, 0xfc00c03f, RD_1|RD_3|SM,           0,              IL3A,           0,      0 },
-{"gssdlc1",            "T,+a(b)",      0xe8000006, 0xfc00c03f, RD_1|RD_3|SM,           0,              IL3A,           0,      0 },
-{"gssdrc1",            "T,+a(b)",      0xe8000007, 0xfc00c03f, RD_1|RD_3|SM,           0,              IL3A,           0,      0 },
-{"gslbx",              "t,+b(b,d)",    0xd8000000, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              IL3A,           0,      0 },
-{"gslhx",              "t,+b(b,d)",    0xd8000001, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              IL3A,           0,      0 },
-{"gslwx",              "t,+b(b,d)",    0xd8000002, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              IL3A,           0,      0 },
-{"gsldx",              "t,+b(b,d)",    0xd8000003, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              IL3A,           0,      0 },
-{"gssbx",              "t,+b(b,d)",    0xf8000000, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              IL3A,           0,      0 },
-{"gsshx",              "t,+b(b,d)",    0xf8000001, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              IL3A,           0,      0 },
-{"gsswx",              "t,+b(b,d)",    0xf8000002, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              IL3A,           0,      0 },
-{"gssdx",              "t,+b(b,d)",    0xf8000003, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              IL3A,           0,      0 },
-{"gslwxc1",            "T,+b(b,d)",    0xd8000006, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              IL3A,           0,      0 },
-{"gsldxc1",            "T,+b(b,d)",    0xd8000007, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              IL3A,           0,      0 },
-{"gsswxc1",            "T,+b(b,d)",    0xf8000006, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              IL3A,           0,      0 },
-{"gssdxc1",            "T,+b(b,d)",    0xf8000007, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              IL3A,           0,      0 },
-{"gslq",               "+z,t,+c(b)",   0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LM,      0,              IL3A,           0,      0 },
-{"gssq",               "+z,t,+c(b)",   0xe8000020, 0xfc008020, RD_1|RD_2|RD_4|SM,      0,              IL3A,           0,      0 },
-{"gslqc1",             "+Z,T,+c(b)",   0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LM,      0,              IL3A,           0,      0 },
-{"gssqc1",             "+Z,T,+c(b)",   0xe8008020, 0xfc008020, RD_1|RD_2|RD_4|SM,      0,              IL3A,           0,      0 },
+{"gsle",               "s,t",          0x70000026, 0xfc00ffff, RD_1|RD_2,              0,              0,              LEXT,   0 },
+{"gsgt",               "s,t",          0x70000027, 0xfc00ffff, RD_1|RD_2,              0,              0,              LEXT,   0 },
+{"gslble",             "t,b,d",        0xc8000010, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gslbgt",             "t,b,d",        0xc8000011, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gslhle",             "t,b,d",        0xc8000012, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gslhgt",             "t,b,d",        0xc8000013, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gslwle",             "t,b,d",        0xc8000014, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gslwgt",             "t,b,d",        0xc8000015, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gsldle",             "t,b,d",        0xc8000016, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gsldgt",             "t,b,d",        0xc8000017, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gssble",             "t,b,d",        0xe8000010, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gssbgt",             "t,b,d",        0xe8000011, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gsshle",             "t,b,d",        0xe8000012, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gsshgt",             "t,b,d",        0xe8000013, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gsswle",             "t,b,d",        0xe8000014, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gsswgt",             "t,b,d",        0xe8000015, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gssdle",             "t,b,d",        0xe8000016, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gssdgt",             "t,b,d",        0xe8000017, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gslwlec1",           "T,b,d",        0xc8000018, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gslwgtc1",           "T,b,d",        0xc8000019, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gsldlec1",           "T,b,d",        0xc800001a, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gsldgtc1",           "T,b,d",        0xc800001b, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              0,              LEXT,   0 },
+{"gsswlec1",           "T,b,d",        0xe800001c, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gsswgtc1",           "T,b,d",        0xe800001d, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gssdlec1",           "T,b,d",        0xe800001e, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gssdgtc1",           "T,b,d",        0xe800001f, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              0,              LEXT,   0 },
+{"gslwlc1",            "T,+a(b)",      0xc8000004, 0xfc00c03f, WR_1|RD_3|LM,           0,              0,              LEXT,   0 },
+{"gslwrc1",            "T,+a(b)",      0xc8000005, 0xfc00c03f, WR_1|RD_3|LM,           0,              0,              LEXT,   0 },
+{"gsldlc1",            "T,+a(b)",      0xc8000006, 0xfc00c03f, WR_1|RD_3|LM,           0,              0,              LEXT,   0 },
+{"gsldrc1",            "T,+a(b)",      0xc8000007, 0xfc00c03f, WR_1|RD_3|LM,           0,              0,              LEXT,   0 },
+{"gsswlc1",            "T,+a(b)",      0xe8000004, 0xfc00c03f, RD_1|RD_3|SM,           0,              0,              LEXT,   0 },
+{"gsswrc1",            "T,+a(b)",      0xe8000005, 0xfc00c03f, RD_1|RD_3|SM,           0,              0,              LEXT,   0 },
+{"gssdlc1",            "T,+a(b)",      0xe8000006, 0xfc00c03f, RD_1|RD_3|SM,           0,              0,              LEXT,   0 },
+{"gssdrc1",            "T,+a(b)",      0xe8000007, 0xfc00c03f, RD_1|RD_3|SM,           0,              0,              LEXT,   0 },
+{"gslbx",              "t,+b(b,d)",    0xd8000000, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              0,              LEXT,   0 },
+{"gslhx",              "t,+b(b,d)",    0xd8000001, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              0,              LEXT,   0 },
+{"gslwx",              "t,+b(b,d)",    0xd8000002, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              0,              LEXT,   0 },
+{"gsldx",              "t,+b(b,d)",    0xd8000003, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              0,              LEXT,   0 },
+{"gssbx",              "t,+b(b,d)",    0xf8000000, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              0,              LEXT,   0 },
+{"gsshx",              "t,+b(b,d)",    0xf8000001, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              0,              LEXT,   0 },
+{"gsswx",              "t,+b(b,d)",    0xf8000002, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              0,              LEXT,   0 },
+{"gssdx",              "t,+b(b,d)",    0xf8000003, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              0,              LEXT,   0 },
+{"gslwxc1",            "T,+b(b,d)",    0xd8000006, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              0,              LEXT,   0 },
+{"gsldxc1",            "T,+b(b,d)",    0xd8000007, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              0,              LEXT,   0 },
+{"gsswxc1",            "T,+b(b,d)",    0xf8000006, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              0,              LEXT,   0 },
+{"gssdxc1",            "T,+b(b,d)",    0xf8000007, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              0,              LEXT,   0 },
+{"gslq",               "+z,t,+c(b)",   0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LM,      0,              0,              LEXT,   0 },
+{"gssq",               "+z,t,+c(b)",   0xe8000020, 0xfc008020, RD_1|RD_2|RD_4|SM,      0,              0,              LEXT,   0 },
+{"gslqc1",             "+Z,T,+c(b)",   0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LM,      0,              0,              LEXT,   0 },
+{"gssqc1",             "+Z,T,+c(b)",   0xe8008020, 0xfc008020, RD_1|RD_2|RD_4|SM,      0,              0,              LEXT,   0 },
 
 /* R5900 VU0 Macromode instructions. */
 {"vabs",               "+7+K,+6+K",      0x4a0001fd, 0xfe0007ff,       CP,             VU0CH,          VU0,            0,      0 },
@@ -1442,7 +1444,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"movf.s",             "D,S,N",        0x46000011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S,   0,              I4_32,          0,      I37 },
 {"movf.ps",            "D,S,N",        0x46c00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,              I5_33,          0,      I37 },
 {"movn",               "d,v,t",        0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I4_32|IL2E|IL2F|EE, 0,  I37 },
-{"movnz",              "d,v,t",        0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E|IL2F|IL3A, 0,      0 },
+{"movnz",              "d,v,t",        0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E|IL2F,      LEXT,   0 },
 {"ffc",                        "d,v",          0x0000000b, 0xfc1f07ff, WR_1|RD_2,              0,              L1,             0,      0 },
 {"movn.d",             "D,S,t",        0x46200013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I4_32,          0,      I37 },
 {"movn.l",             "D,S,t",        0x46a00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
@@ -2441,40 +2443,40 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* ST Microelectronics Loongson-2E and -2F.  */
 {"mult.g",             "d,s,t",        0x7c000018, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"mult.g",             "d,s,t",        0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsmult",             "d,s,t",        0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsmult",             "d,s,t",        0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"multu.g",            "d,s,t",        0x7c000019, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"multu.g",            "d,s,t",        0x70000012, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsmultu",            "d,s,t",        0x70000012, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsmultu",            "d,s,t",        0x70000012, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"dmult.g",            "d,s,t",        0x7c00001c, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"dmult.g",            "d,s,t",        0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsdmult",            "d,s,t",        0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsdmult",            "d,s,t",        0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"dmultu.g",           "d,s,t",        0x7c00001d, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"dmultu.g",           "d,s,t",        0x70000013, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsdmultu",           "d,s,t",        0x70000013, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsdmultu",           "d,s,t",        0x70000013, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"div.g",              "d,s,t",        0x7c00001a, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"div.g",              "d,s,t",        0x70000014, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsdiv",              "d,s,t",        0x70000014, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsdiv",              "d,s,t",        0x70000014, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"divu.g",             "d,s,t",        0x7c00001b, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"divu.g",             "d,s,t",        0x70000016, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsdivu",             "d,s,t",        0x70000016, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsdivu",             "d,s,t",        0x70000016, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"ddiv.g",             "d,s,t",        0x7c00001e, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"ddiv.g",             "d,s,t",        0x70000015, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsddiv",             "d,s,t",        0x70000015, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsddiv",             "d,s,t",        0x70000015, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"ddivu.g",            "d,s,t",        0x7c00001f, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"ddivu.g",            "d,s,t",        0x70000017, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsddivu",            "d,s,t",        0x70000017, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsddivu",            "d,s,t",        0x70000017, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"mod.g",              "d,s,t",        0x7c000022, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"mod.g",              "d,s,t",        0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsmod",              "d,s,t",        0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsmod",              "d,s,t",        0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"modu.g",             "d,s,t",        0x7c000023, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"modu.g",             "d,s,t",        0x7000001e, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsmodu",             "d,s,t",        0x7000001e, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsmodu",             "d,s,t",        0x7000001e, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"dmod.g",             "d,s,t",        0x7c000026, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"dmod.g",             "d,s,t",        0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsdmod",             "d,s,t",        0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsdmod",             "d,s,t",        0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"dmodu.g",            "d,s,t",        0x7c000027, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"dmodu.g",            "d,s,t",        0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
-{"gsdmodu",            "d,s,t",        0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
+{"gsdmodu",            "d,s,t",        0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              LEXT,   0 },
 {"packsshb",           "D,S,T",        0x47400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
 {"packsshb",           "D,S,T",        0x4b400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"packsswh",           "D,S,T",        0x47200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },