drm/amd/display: Disable dpstreamclk, symclk32_se, and symclk32_le

[Why & How]
Disable dpstreamclk, symclk32_se, and symclk32_le when not in use.

Reviewed-by: Ariel Bernstein <eric.yang2@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index f6f2d48..4098669 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -178,7 +178,16 @@
        type DSCCLK2_DTO_MODULO;\
        type DSCCLK0_DTO_ENABLE;\
        type DSCCLK1_DTO_ENABLE;\
-       type DSCCLK2_DTO_ENABLE;
+       type DSCCLK2_DTO_ENABLE;\
+       type SYMCLK32_ROOT_SE0_GATE_DISABLE;\
+       type SYMCLK32_ROOT_SE1_GATE_DISABLE;\
+       type SYMCLK32_ROOT_SE2_GATE_DISABLE;\
+       type SYMCLK32_ROOT_SE3_GATE_DISABLE;\
+       type SYMCLK32_ROOT_LE0_GATE_DISABLE;\
+       type SYMCLK32_ROOT_LE1_GATE_DISABLE;\
+       type DPSTREAMCLK_ROOT_GATE_DISABLE;\
+       type DPSTREAMCLK_GATE_DISABLE;
+
 
 
 struct dccg_shift {
@@ -219,6 +228,10 @@ struct dccg_registers {
        uint32_t DSCCLK0_DTO_PARAM;
        uint32_t DSCCLK1_DTO_PARAM;
        uint32_t DSCCLK2_DTO_PARAM;
+       uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE;
+       uint32_t DPSTREAMCLK_GATE_DISABLE;
+       uint32_t DCCG_GATE_DISABLE_CNTL3;
+
 };
 
 struct dcn_dccg {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 3a325e4..815481a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -94,10 +94,7 @@ static enum phyd32clk_clock_source get_phy_mux_symclk(
        return src;
 }
 
-void dccg31_set_dpstreamclk(
-               struct dccg *dccg,
-               enum hdmistreamclk_source src,
-               int otg_inst)
+static void dccg31_enable_dpstreamclk(struct dccg *dccg, int otg_inst)
 {
        struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 
@@ -105,24 +102,69 @@ void dccg31_set_dpstreamclk(
        switch (otg_inst) {
        case 0:
                REG_UPDATE(DPSTREAMCLK_CNTL,
-                               DPSTREAMCLK_PIPE0_EN, (src == REFCLK) ? 0 : 1);
+                               DPSTREAMCLK_PIPE0_EN, 1);
                break;
        case 1:
                REG_UPDATE(DPSTREAMCLK_CNTL,
-                               DPSTREAMCLK_PIPE1_EN, (src == REFCLK) ? 0 : 1);
+                               DPSTREAMCLK_PIPE1_EN, 1);
                break;
        case 2:
                REG_UPDATE(DPSTREAMCLK_CNTL,
-                               DPSTREAMCLK_PIPE2_EN, (src == REFCLK) ? 0 : 1);
+                               DPSTREAMCLK_PIPE2_EN, 1);
                break;
        case 3:
                REG_UPDATE(DPSTREAMCLK_CNTL,
-                               DPSTREAMCLK_PIPE3_EN, (src == REFCLK) ? 0 : 1);
+                               DPSTREAMCLK_PIPE3_EN, 1);
                break;
        default:
                BREAK_TO_DEBUGGER();
                return;
        }
+       if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
+               REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                       DPSTREAMCLK_ROOT_GATE_DISABLE, 1);
+}
+
+static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst)
+{
+       struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+       if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
+               REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                               DPSTREAMCLK_ROOT_GATE_DISABLE, 0);
+
+       switch (otg_inst) {
+       case 0:
+               REG_UPDATE(DPSTREAMCLK_CNTL,
+                               DPSTREAMCLK_PIPE0_EN, 0);
+               break;
+       case 1:
+               REG_UPDATE(DPSTREAMCLK_CNTL,
+                               DPSTREAMCLK_PIPE1_EN, 0);
+               break;
+       case 2:
+               REG_UPDATE(DPSTREAMCLK_CNTL,
+                               DPSTREAMCLK_PIPE2_EN, 0);
+               break;
+       case 3:
+               REG_UPDATE(DPSTREAMCLK_CNTL,
+                               DPSTREAMCLK_PIPE3_EN, 0);
+               break;
+       default:
+               BREAK_TO_DEBUGGER();
+               return;
+       }
+}
+
+void dccg31_set_dpstreamclk(
+               struct dccg *dccg,
+               enum hdmistreamclk_source src,
+               int otg_inst)
+{
+       if (src == REFCLK)
+               dccg31_disable_dpstreamclk(dccg, otg_inst);
+       else
+               dccg31_enable_dpstreamclk(dccg, otg_inst);
 }
 
 void dccg31_enable_symclk32_se(
@@ -137,21 +179,33 @@ void dccg31_enable_symclk32_se(
        /* select one of the PHYD32CLKs as the source for symclk32_se */
        switch (hpo_se_inst) {
        case 0:
+               if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_ROOT_SE0_GATE_DISABLE, 1);
                REG_UPDATE_2(SYMCLK32_SE_CNTL,
                                SYMCLK32_SE0_SRC_SEL, phyd32clk,
                                SYMCLK32_SE0_EN, 1);
                break;
        case 1:
+               if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_ROOT_SE1_GATE_DISABLE, 1);
                REG_UPDATE_2(SYMCLK32_SE_CNTL,
                                SYMCLK32_SE1_SRC_SEL, phyd32clk,
                                SYMCLK32_SE1_EN, 1);
                break;
        case 2:
+               if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_ROOT_SE2_GATE_DISABLE, 1);
                REG_UPDATE_2(SYMCLK32_SE_CNTL,
                                SYMCLK32_SE2_SRC_SEL, phyd32clk,
                                SYMCLK32_SE2_EN, 1);
                break;
        case 3:
+               if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_ROOT_SE3_GATE_DISABLE, 1);
                REG_UPDATE_2(SYMCLK32_SE_CNTL,
                                SYMCLK32_SE3_SRC_SEL, phyd32clk,
                                SYMCLK32_SE3_EN, 1);
@@ -174,21 +228,33 @@ void dccg31_disable_symclk32_se(
                REG_UPDATE_2(SYMCLK32_SE_CNTL,
                                SYMCLK32_SE0_SRC_SEL, 0,
                                SYMCLK32_SE0_EN, 0);
+               if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_ROOT_SE0_GATE_DISABLE, 0);
                break;
        case 1:
                REG_UPDATE_2(SYMCLK32_SE_CNTL,
                                SYMCLK32_SE1_SRC_SEL, 0,
                                SYMCLK32_SE1_EN, 0);
+               if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_ROOT_SE1_GATE_DISABLE, 0);
                break;
        case 2:
                REG_UPDATE_2(SYMCLK32_SE_CNTL,
                                SYMCLK32_SE2_SRC_SEL, 0,
                                SYMCLK32_SE2_EN, 0);
+               if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_ROOT_SE2_GATE_DISABLE, 0);
                break;
        case 3:
                REG_UPDATE_2(SYMCLK32_SE_CNTL,
                                SYMCLK32_SE3_SRC_SEL, 0,
                                SYMCLK32_SE3_EN, 0);
+               if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_ROOT_SE3_GATE_DISABLE, 0);
                break;
        default:
                BREAK_TO_DEBUGGER();
@@ -208,11 +274,17 @@ void dccg31_enable_symclk32_le(
        /* select one of the PHYD32CLKs as the source for symclk32_le */
        switch (hpo_le_inst) {
        case 0:
+               if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_ROOT_LE0_GATE_DISABLE, 1);
                REG_UPDATE_2(SYMCLK32_LE_CNTL,
                                SYMCLK32_LE0_SRC_SEL, phyd32clk,
                                SYMCLK32_LE0_EN, 1);
                break;
        case 1:
+               if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_ROOT_LE1_GATE_DISABLE, 1);
                REG_UPDATE_2(SYMCLK32_LE_CNTL,
                                SYMCLK32_LE1_SRC_SEL, phyd32clk,
                                SYMCLK32_LE1_EN, 1);
@@ -235,11 +307,17 @@ void dccg31_disable_symclk32_le(
                REG_UPDATE_2(SYMCLK32_LE_CNTL,
                                SYMCLK32_LE0_SRC_SEL, 0,
                                SYMCLK32_LE0_EN, 0);
+               if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_ROOT_LE0_GATE_DISABLE, 0);
                break;
        case 1:
                REG_UPDATE_2(SYMCLK32_LE_CNTL,
                                SYMCLK32_LE1_SRC_SEL, 0,
                                SYMCLK32_LE1_EN, 0);
+               if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_ROOT_LE1_GATE_DISABLE, 0);
                break;
        default:
                BREAK_TO_DEBUGGER();
@@ -524,6 +602,19 @@ void dccg31_init(struct dccg *dccg)
        dccg31_disable_symclk32_se(dccg, 1);
        dccg31_disable_symclk32_se(dccg, 2);
        dccg31_disable_symclk32_se(dccg, 3);
+
+       if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) {
+               dccg31_disable_symclk32_le(dccg, 0);
+               dccg31_disable_symclk32_le(dccg, 1);
+       }
+
+       if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {
+               dccg31_disable_dpstreamclk(dccg, 0);
+               dccg31_disable_dpstreamclk(dccg, 1);
+               dccg31_disable_dpstreamclk(dccg, 2);
+               dccg31_disable_dpstreamclk(dccg, 3);
+       }
+
 }
 
 static const struct dccg_funcs dccg31_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
index 61b457a..602bf46 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
@@ -65,7 +65,8 @@
        SR(DSCCLK0_DTO_PARAM),\
        SR(DSCCLK1_DTO_PARAM),\
        SR(DSCCLK2_DTO_PARAM),\
-       SR(DSCCLK_DTO_CTRL)
+       SR(DSCCLK_DTO_CTRL),\
+       SR(DCCG_GATE_DISABLE_CNTL3)
 
 
 #define DCCG_MASK_SH_LIST_DCN31(mask_sh) \
@@ -132,7 +133,16 @@
        DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_MODULO, mask_sh),\
        DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_DTO_ENABLE, mask_sh),\
        DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_DTO_ENABLE, mask_sh),\
-       DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_DTO_ENABLE, mask_sh)
+       DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_DTO_ENABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_ROOT_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh)
+
 
 
 
@@ -144,6 +154,11 @@ struct dccg *dccg31_create(
 
 void dccg31_init(struct dccg *dccg);
 
+void dccg31_set_dpstreamclk(
+               struct dccg *dccg,
+               enum hdmistreamclk_source src,
+               int otg_inst);
+
 void dccg31_enable_symclk32_se(
                struct dccg *dccg,
                int hpo_se_inst,