#endif
/*
- * Inserts a specific DisplayLink controller command into the provided
- * buffer.
+ * All DisplayLink bulk operations start with 0xAF, followed by specific code
+ * All operations are written to buffers which then later get sent to device
*/
static char *dlfb_set_register(char *buf, u8 reg, u8 val)
{
return dlfb_set_register(wrptr, 0x22, base);
}
+/*
+ * DisplayLink HW has separate 16bpp and 8bpp framebuffers.
+ * In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer
+ */
static char *dlfb_set_base8bpp(char *wrptr, u32 base)
{
wrptr = dlfb_set_register(wrptr, 0x26, base >> 16);
* same actual count. This makes sense once you read above a couple of
* times and think about it from a hardware perspective.
*/
-static u16 lfsr16(u16 actual_count)
+static u16 dlfb_lfsr16(u16 actual_count)
{
u32 lv = 0xFFFF; /* This is the lfsr value that the hw starts with */
*/
static char *dlfb_set_register_lfsr16(char *wrptr, u8 reg, u16 value)
{
- return dlfb_set_register_16(wrptr, reg, lfsr16(value));
+ return dlfb_set_register_16(wrptr, reg, dlfb_lfsr16(value));
}
/*
unsigned long size = vma->vm_end - vma->vm_start;
unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
unsigned long page, pos;
+ struct dlfb_data *dev = info->par;
- printk("MMAP: %lu %u\n", offset + size, info->fix.smem_len);
+ dl_notice("MMAP: %lu %u\n", offset + size, info->fix.smem_len);
if (offset + size > info->fix.smem_len)
return -EINVAL;