include: Add guest external interrupt related defines
authorAnup Patel <anup.patel@wdc.com>
Thu, 12 Dec 2019 17:35:03 +0000 (23:05 +0530)
committerAnup Patel <anup@brainfault.org>
Mon, 16 Dec 2019 09:18:12 +0000 (14:48 +0530)
With RISC-V H-extension v0.5 draft, we have special support for guest
external interrupts so this patch adds related defines which were
missed-out previously.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
include/sbi/riscv_encoding.h

index 316d743..6dd0d30 100644 (file)
@@ -78,6 +78,7 @@
 #define IRQ_S_EXT                      9
 #define IRQ_VS_EXT                     10
 #define IRQ_M_EXT                      11
+#define IRQ_S_GEXT                     12
 
 #define MIP_SSIP                       (_UL(1) << IRQ_S_SOFT)
 #define MIP_VSSIP                      (_UL(1) << IRQ_VS_SOFT)
@@ -88,6 +89,7 @@
 #define MIP_SEIP                       (_UL(1) << IRQ_S_EXT)
 #define MIP_VSEIP                      (_UL(1) << IRQ_VS_EXT)
 #define MIP_MEIP                       (_UL(1) << IRQ_M_EXT)
+#define MIP_SGEIP                      (_UL(1) << IRQ_S_GEXT)
 
 #define SIP_SSIP                       MIP_SSIP
 #define SIP_STIP                       MIP_STIP
 #define CSR_HTIMEDELTA                 0x605
 #define CSR_HTIMEDELTAH                        0x615
 #define CSR_HCOUNTERNEN                        0x606
+#define CSR_HGEIE                      0x607
 #define CSR_HTVAL                      0x643
 #define CSR_HIP                                0x644
 #define CSR_HTINST                     0x64a
 #define CSR_HGATP                      0x680
+#define CSR_HGEIP                      0xe07
 
 #define CSR_VSSTATUS                   0x200
 #define CSR_VSIE                       0x204