[InstCombine] Add tests for add+icmp assumes (NFC)

diff --git a/llvm/test/Transforms/InstCombine/assume.ll b/llvm/test/Transforms/InstCombine/assume.ll
index d11928f..1c73d86 100644 (file)
--- a/llvm/test/Transforms/InstCombine/assume.ll
+++ b/llvm/test/Transforms/InstCombine/assume.ll
@@ -837,6 +837,125 @@ define void @assume_makes_and_known_assume_on_bitwise(ptr %p, i32 %a, i32 %b) {
   ret void
 }
 
+define i32 @range_16_31_top28(i32 %x) {
+; CHECK-LABEL: @range_16_31_top28(
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], -16
+; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP1]], 16
+; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    ret i32 16
+;
+  %add = add i32 %x, -16
+  %cmp = icmp ult i32 %add, 16
+  call void @llvm.assume(i1 %cmp)
+  %res = and i32 %x, u0xfffffff0
+  ret i32 %res
+}
+
+define i32 @range_16_31_top29(i32 %x) {
+; CHECK-LABEL: @range_16_31_top29(
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], -16
+; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP1]], 16
+; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    [[RES:%.*]] = and i32 [[X]], 24
+; CHECK-NEXT:    ret i32 [[RES]]
+;
+  %add = add i32 %x, -16
+  %cmp = icmp ult i32 %add, 16
+  call void @llvm.assume(i1 %cmp)
+  %res = and i32 %x, u0xfffffff8
+  ret i32 %res
+}
+
+define i32 @range_16_30_top28(i32 %x) {
+; CHECK-LABEL: @range_16_30_top28(
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[X:%.*]], -16
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[ADD]], 15
+; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    [[RES:%.*]] = and i32 [[X]], -16
+; CHECK-NEXT:    ret i32 [[RES]]
+;
+  %add = add i32 %x, -16
+  %cmp = icmp ult i32 %add, 15
+  call void @llvm.assume(i1 %cmp)
+  %res = and i32 %x, u0xfffffff0
+  ret i32 %res
+}
+
+define i32 @range_16_32_top28(i32 %x) {
+; CHECK-LABEL: @range_16_32_top28(
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[X:%.*]], -16
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[ADD]], 17
+; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    [[RES:%.*]] = and i32 [[X]], -16
+; CHECK-NEXT:    ret i32 [[RES]]
+;
+  %add = add i32 %x, -16
+  %cmp = icmp ult i32 %add, 17
+  call void @llvm.assume(i1 %cmp)
+  %res = and i32 %x, u0xfffffff0
+  ret i32 %res
+}
+
+define i32 @range_16_32_top27(i32 %x) {
+; CHECK-LABEL: @range_16_32_top27(
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[X:%.*]], -16
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[ADD]], 17
+; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    [[RES:%.*]] = and i32 [[X]], -32
+; CHECK-NEXT:    ret i32 [[RES]]
+;
+  %add = add i32 %x, -16
+  %cmp = icmp ult i32 %add, 17
+  call void @llvm.assume(i1 %cmp)
+  %res = and i32 %x, u0xffffffe0
+  ret i32 %res
+}
+
+define i32 @range_16_32_top26(i32 %x) {
+; CHECK-LABEL: @range_16_32_top26(
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[X:%.*]], -16
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[ADD]], 17
+; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    [[RES:%.*]] = and i32 [[X]], -64
+; CHECK-NEXT:    ret i32 [[RES]]
+;
+  %add = add i32 %x, -16
+  %cmp = icmp ult i32 %add, 17
+  call void @llvm.assume(i1 %cmp)
+  %res = and i32 %x, u0xffffffc0
+  ret i32 %res
+}
+
+define i32 @range_15_31_top28(i32 %x) {
+; CHECK-LABEL: @range_15_31_top28(
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[X:%.*]], -15
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[ADD]], 16
+; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    [[RES:%.*]] = and i32 [[X]], -16
+; CHECK-NEXT:    ret i32 [[RES]]
+;
+  %add = add i32 %x, -15
+  %cmp = icmp ult i32 %add, 16
+  call void @llvm.assume(i1 %cmp)
+  %res = and i32 %x, u0xfffffff0
+  ret i32 %res
+}
+
+define i32 @range_15_31_top27(i32 %x) {
+; CHECK-LABEL: @range_15_31_top27(
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[X:%.*]], -15
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[ADD]], 16
+; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    [[RES:%.*]] = and i32 [[X]], -32
+; CHECK-NEXT:    ret i32 [[RES]]
+;
+  %add = add i32 %x, -15
+  %cmp = icmp ult i32 %add, 16
+  call void @llvm.assume(i1 %cmp)
+  %res = and i32 %x, u0xffffffe0
+  ret i32 %res
+}
+
 declare void @llvm.dbg.value(metadata, metadata, metadata)
 
 !llvm.dbg.cu = !{!0}