crypto: qat - add support for shared ustore
authorJack Xu <jack.xu@intel.com>
Fri, 6 Nov 2020 11:28:08 +0000 (19:28 +0800)
committerHerbert Xu <herbert@gondor.apana.org.au>
Fri, 13 Nov 2020 09:38:54 +0000 (20:38 +1100)
Add support for shared ustore mode support. This is required by the next
generation of QAT devices to share the same fw image across engines.

Signed-off-by: Jack Xu <jack.xu@intel.com>
Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com>
Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h
drivers/crypto/qat/qat_common/qat_hal.c
drivers/crypto/qat/qat_common/qat_uclo.c

index cc9b83d..5b9f2e8 100644 (file)
@@ -34,6 +34,7 @@ struct icp_qat_fw_loader_chip_info {
        u32 wakeup_event_val;
        bool fw_auth;
        bool css_3k;
+       bool tgroup_share_ustore;
        u32 fcu_ctl_csr;
        u32 fcu_sts_csr;
        u32 fcu_dram_addr_hi;
index 94c0b04..6ccfb8c 100644 (file)
@@ -707,6 +707,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
                handle->chip_info->wakeup_event_val = WAKEUP_EVENT;
                handle->chip_info->fw_auth = true;
                handle->chip_info->css_3k = false;
+               handle->chip_info->tgroup_share_ustore = false;
                handle->chip_info->fcu_ctl_csr = FCU_CONTROL;
                handle->chip_info->fcu_sts_csr = FCU_STATUS;
                handle->chip_info->fcu_dram_addr_hi = FCU_DRAM_ADDR_HI;
@@ -725,6 +726,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
                handle->chip_info->wakeup_event_val = WAKEUP_EVENT;
                handle->chip_info->fw_auth = false;
                handle->chip_info->css_3k = false;
+               handle->chip_info->tgroup_share_ustore = false;
                handle->chip_info->fcu_ctl_csr = 0;
                handle->chip_info->fcu_sts_csr = 0;
                handle->chip_info->fcu_dram_addr_hi = 0;
index c6b309d..b280fb0 100644 (file)
@@ -1180,21 +1180,24 @@ static int qat_uclo_map_suof(struct icp_qat_fw_loader_handle *handle,
                if (!suof_img_hdr)
                        return -ENOMEM;
                suof_handle->img_table.simg_hdr = suof_img_hdr;
-       }
 
-       for (i = 0; i < suof_handle->img_table.num_simgs; i++) {
-               qat_uclo_map_simg(handle, &suof_img_hdr[i],
-                                 &suof_chunk_hdr[1 + i]);
-               ret = qat_uclo_check_simg_compat(handle,
-                                                &suof_img_hdr[i]);
-               if (ret)
-                       return ret;
-               suof_img_hdr[i].ae_mask &= handle->cfg_ae_mask;
-               if ((suof_img_hdr[i].ae_mask & 0x1) != 0)
-                       ae0_img = i;
+               for (i = 0; i < suof_handle->img_table.num_simgs; i++) {
+                       qat_uclo_map_simg(handle, &suof_img_hdr[i],
+                                         &suof_chunk_hdr[1 + i]);
+                       ret = qat_uclo_check_simg_compat(handle,
+                                                        &suof_img_hdr[i]);
+                       if (ret)
+                               return ret;
+                       suof_img_hdr[i].ae_mask &= handle->cfg_ae_mask;
+                       if ((suof_img_hdr[i].ae_mask & 0x1) != 0)
+                               ae0_img = i;
+               }
+
+               if (!handle->chip_info->tgroup_share_ustore) {
+                       qat_uclo_tail_img(suof_img_hdr, ae0_img,
+                                         suof_handle->img_table.num_simgs);
+               }
        }
-       qat_uclo_tail_img(suof_img_hdr, ae0_img,
-                         suof_handle->img_table.num_simgs);
        return 0;
 }