[codeview] Use push_macro to avoid conflicts instead of a prefix

Summary:
This prefix was added in r333421, and it changed our dumper output to
say things like "CVRegEAX" instead of just "EAX". That's a functional
change that I'd rather avoid.

I tested GCC, Clang, and MSVC, and all of them support #pragma
push_macro. They don't issue warnings whem the macro is not defined
either.

I don't have a Mac so I can't test the real termios.h header, but I
looked at the termios.h sources online and looked for other conflicts.
I saw only the CR* macros, so those are the ones we work around.

Reviewers: zturner, JDevlieghere

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D50851

llvm-svn: 339907

diff --git a/lld/test/COFF/pdb-type-server-simple.test b/lld/test/COFF/pdb-type-server-simple.test
index 51a92db..cae32af 100644 (file)
--- a/lld/test/COFF/pdb-type-server-simple.test
+++ b/lld/test/COFF/pdb-type-server-simple.test
@@ -89,7 +89,7 @@ CHECK:            size = 0, padding size = 0, offset to padding = 0
 CHECK:            bytes of callee saved registers = 0, exception handler addr = 0000:0000
 CHECK:            flags = has async eh | opt speed
 CHECK:      180 | S_REGREL32 [size = 16] `p`
-CHECK:            type = [[FOO_PTR]] (Foo*), register = CVRegRSP, offset = 8
+CHECK:            type = [[FOO_PTR]] (Foo*), register = RSP, offset = 8
 CHECK:      196 | S_END [size = 4]
 CHECK:      200 | S_BUILDINFO [size = 8] BuildId = `[[B_BUILD]]`
 CHECK-LABEL:   Mod 0002 | `* Linker *`:

diff --git a/llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def b/llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def
index dfb579c..cd07344 100644 (file)
--- a/llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def
+++ b/llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def
@@ -18,310 +18,325 @@
 // This currently only contains the "register subset shared by all processor
 // types" (ERR etc.) and the x86 registers.
 
-CV_REGISTER(CVRegERR, 30000)
-CV_REGISTER(CVRegTEB, 30001)
-CV_REGISTER(CVRegTIMER, 30002)
-CV_REGISTER(CVRegEFAD1, 30003)
-CV_REGISTER(CVRegEFAD2, 30004)
-CV_REGISTER(CVRegEFAD3, 30005)
-CV_REGISTER(CVRegVFRAME, 30006)
-CV_REGISTER(CVRegHANDLE, 30007)
-CV_REGISTER(CVRegPARAMS, 30008)
-CV_REGISTER(CVRegLOCALS, 30009)
-CV_REGISTER(CVRegTID, 30010)
-CV_REGISTER(CVRegENV, 30011)
-CV_REGISTER(CVRegCMDLN, 30012)
+// Some system headers define macros that conflict with our enums. Every
+// compiler supported by LLVM has the push_macro and pop_macro pragmas, so use
+// them to avoid the conflict.
+#pragma push_macro("CR0")
+#pragma push_macro("CR1")
+#pragma push_macro("CR2")
+#pragma push_macro("CR3")
+#pragma push_macro("CR4")
 
-CV_REGISTER(CVRegNONE, 0)
-CV_REGISTER(CVRegAL, 1)
-CV_REGISTER(CVRegCL, 2)
-CV_REGISTER(CVRegDL, 3)
-CV_REGISTER(CVRegBL, 4)
-CV_REGISTER(CVRegAH, 5)
-CV_REGISTER(CVRegCH, 6)
-CV_REGISTER(CVRegDH, 7)
-CV_REGISTER(CVRegBH, 8)
-CV_REGISTER(CVRegAX, 9)
-CV_REGISTER(CVRegCX, 10)
-CV_REGISTER(CVRegDX, 11)
-CV_REGISTER(CVRegBX, 12)
-CV_REGISTER(CVRegSP, 13)
-CV_REGISTER(CVRegBP, 14)
-CV_REGISTER(CVRegSI, 15)
-CV_REGISTER(CVRegDI, 16)
-CV_REGISTER(CVRegEAX, 17)
-CV_REGISTER(CVRegECX, 18)
-CV_REGISTER(CVRegEDX, 19)
-CV_REGISTER(CVRegEBX, 20)
-CV_REGISTER(CVRegESP, 21)
-CV_REGISTER(CVRegEBP, 22)
-CV_REGISTER(CVRegESI, 23)
-CV_REGISTER(CVRegEDI, 24)
-CV_REGISTER(CVRegES, 25)
-CV_REGISTER(CVRegCS, 26)
-CV_REGISTER(CVRegSS, 27)
-CV_REGISTER(CVRegDS, 28)
-CV_REGISTER(CVRegFS, 29)
-CV_REGISTER(CVRegGS, 30)
-CV_REGISTER(CVRegIP, 31)
-CV_REGISTER(CVRegFLAGS, 32)
-CV_REGISTER(CVRegEIP, 33)
-CV_REGISTER(CVRegEFLAGS, 34)
-CV_REGISTER(CVRegTEMP, 40)
-CV_REGISTER(CVRegTEMPH, 41)
-CV_REGISTER(CVRegQUOTE, 42)
-CV_REGISTER(CVRegPCDR3, 43)
-CV_REGISTER(CVRegPCDR4, 44)
-CV_REGISTER(CVRegPCDR5, 45)
-CV_REGISTER(CVRegPCDR6, 46)
-CV_REGISTER(CVRegPCDR7, 47)
-CV_REGISTER(CVRegCR0, 80)
-CV_REGISTER(CVRegCR1, 81)
-CV_REGISTER(CVRegCR2, 82)
-CV_REGISTER(CVRegCR3, 83)
-CV_REGISTER(CVRegCR4, 84)
-CV_REGISTER(CVRegDR0, 90)
-CV_REGISTER(CVRegDR1, 91)
-CV_REGISTER(CVRegDR2, 92)
-CV_REGISTER(CVRegDR3, 93)
-CV_REGISTER(CVRegDR4, 94)
-CV_REGISTER(CVRegDR5, 95)
-CV_REGISTER(CVRegDR6, 96)
-CV_REGISTER(CVRegDR7, 97)
-CV_REGISTER(CVRegGDTR, 110)
-CV_REGISTER(CVRegGDTL, 111)
-CV_REGISTER(CVRegIDTR, 112)
-CV_REGISTER(CVRegIDTL, 113)
-CV_REGISTER(CVRegLDTR, 114)
-CV_REGISTER(CVRegTR, 115)
+CV_REGISTER(ERR, 30000)
+CV_REGISTER(TEB, 30001)
+CV_REGISTER(TIMER, 30002)
+CV_REGISTER(EFAD1, 30003)
+CV_REGISTER(EFAD2, 30004)
+CV_REGISTER(EFAD3, 30005)
+CV_REGISTER(VFRAME, 30006)
+CV_REGISTER(HANDLE, 30007)
+CV_REGISTER(PARAMS, 30008)
+CV_REGISTER(LOCALS, 30009)
+CV_REGISTER(TID, 30010)
+CV_REGISTER(ENV, 30011)
+CV_REGISTER(CMDLN, 30012)
 
-CV_REGISTER(CVRegPSEUDO1, 116)
-CV_REGISTER(CVRegPSEUDO2, 117)
-CV_REGISTER(CVRegPSEUDO3, 118)
-CV_REGISTER(CVRegPSEUDO4, 119)
-CV_REGISTER(CVRegPSEUDO5, 120)
-CV_REGISTER(CVRegPSEUDO6, 121)
-CV_REGISTER(CVRegPSEUDO7, 122)
-CV_REGISTER(CVRegPSEUDO8, 123)
-CV_REGISTER(CVRegPSEUDO9, 124)
+CV_REGISTER(NONE, 0)
+CV_REGISTER(AL, 1)
+CV_REGISTER(CL, 2)
+CV_REGISTER(DL, 3)
+CV_REGISTER(BL, 4)
+CV_REGISTER(AH, 5)
+CV_REGISTER(CH, 6)
+CV_REGISTER(DH, 7)
+CV_REGISTER(BH, 8)
+CV_REGISTER(AX, 9)
+CV_REGISTER(CX, 10)
+CV_REGISTER(DX, 11)
+CV_REGISTER(BX, 12)
+CV_REGISTER(SP, 13)
+CV_REGISTER(BP, 14)
+CV_REGISTER(SI, 15)
+CV_REGISTER(DI, 16)
+CV_REGISTER(EAX, 17)
+CV_REGISTER(ECX, 18)
+CV_REGISTER(EDX, 19)
+CV_REGISTER(EBX, 20)
+CV_REGISTER(ESP, 21)
+CV_REGISTER(EBP, 22)
+CV_REGISTER(ESI, 23)
+CV_REGISTER(EDI, 24)
+CV_REGISTER(ES, 25)
+CV_REGISTER(CS, 26)
+CV_REGISTER(SS, 27)
+CV_REGISTER(DS, 28)
+CV_REGISTER(FS, 29)
+CV_REGISTER(GS, 30)
+CV_REGISTER(IP, 31)
+CV_REGISTER(FLAGS, 32)
+CV_REGISTER(EIP, 33)
+CV_REGISTER(EFLAGS, 34)
+CV_REGISTER(TEMP, 40)
+CV_REGISTER(TEMPH, 41)
+CV_REGISTER(QUOTE, 42)
+CV_REGISTER(PCDR3, 43)
+CV_REGISTER(PCDR4, 44)
+CV_REGISTER(PCDR5, 45)
+CV_REGISTER(PCDR6, 46)
+CV_REGISTER(PCDR7, 47)
+CV_REGISTER(CR0, 80)
+CV_REGISTER(CR1, 81)
+CV_REGISTER(CR2, 82)
+CV_REGISTER(CR3, 83)
+CV_REGISTER(CR4, 84)
+CV_REGISTER(DR0, 90)
+CV_REGISTER(DR1, 91)
+CV_REGISTER(DR2, 92)
+CV_REGISTER(DR3, 93)
+CV_REGISTER(DR4, 94)
+CV_REGISTER(DR5, 95)
+CV_REGISTER(DR6, 96)
+CV_REGISTER(DR7, 97)
+CV_REGISTER(GDTR, 110)
+CV_REGISTER(GDTL, 111)
+CV_REGISTER(IDTR, 112)
+CV_REGISTER(IDTL, 113)
+CV_REGISTER(LDTR, 114)
+CV_REGISTER(TR, 115)
 
-CV_REGISTER(CVRegST0, 128)
-CV_REGISTER(CVRegST1, 129)
-CV_REGISTER(CVRegST2, 130)
-CV_REGISTER(CVRegST3, 131)
-CV_REGISTER(CVRegST4, 132)
-CV_REGISTER(CVRegST5, 133)
-CV_REGISTER(CVRegST6, 134)
-CV_REGISTER(CVRegST7, 135)
-CV_REGISTER(CVRegCTRL, 136)
-CV_REGISTER(CVRegSTAT, 137)
-CV_REGISTER(CVRegTAG, 138)
-CV_REGISTER(CVRegFPIP, 139)
-CV_REGISTER(CVRegFPCS, 140)
-CV_REGISTER(CVRegFPDO, 141)
-CV_REGISTER(CVRegFPDS, 142)
-CV_REGISTER(CVRegISEM, 143)
-CV_REGISTER(CVRegFPEIP, 144)
-CV_REGISTER(CVRegFPEDO, 145)
+CV_REGISTER(PSEUDO1, 116)
+CV_REGISTER(PSEUDO2, 117)
+CV_REGISTER(PSEUDO3, 118)
+CV_REGISTER(PSEUDO4, 119)
+CV_REGISTER(PSEUDO5, 120)
+CV_REGISTER(PSEUDO6, 121)
+CV_REGISTER(PSEUDO7, 122)
+CV_REGISTER(PSEUDO8, 123)
+CV_REGISTER(PSEUDO9, 124)
 
-CV_REGISTER(CVRegMM0, 146)
-CV_REGISTER(CVRegMM1, 147)
-CV_REGISTER(CVRegMM2, 148)
-CV_REGISTER(CVRegMM3, 149)
-CV_REGISTER(CVRegMM4, 150)
-CV_REGISTER(CVRegMM5, 151)
-CV_REGISTER(CVRegMM6, 152)
-CV_REGISTER(CVRegMM7, 153)
+CV_REGISTER(ST0, 128)
+CV_REGISTER(ST1, 129)
+CV_REGISTER(ST2, 130)
+CV_REGISTER(ST3, 131)
+CV_REGISTER(ST4, 132)
+CV_REGISTER(ST5, 133)
+CV_REGISTER(ST6, 134)
+CV_REGISTER(ST7, 135)
+CV_REGISTER(CTRL, 136)
+CV_REGISTER(STAT, 137)
+CV_REGISTER(TAG, 138)
+CV_REGISTER(FPIP, 139)
+CV_REGISTER(FPCS, 140)
+CV_REGISTER(FPDO, 141)
+CV_REGISTER(FPDS, 142)
+CV_REGISTER(ISEM, 143)
+CV_REGISTER(FPEIP, 144)
+CV_REGISTER(FPEDO, 145)
 
-CV_REGISTER(CVRegXMM0, 154)
-CV_REGISTER(CVRegXMM1, 155)
-CV_REGISTER(CVRegXMM2, 156)
-CV_REGISTER(CVRegXMM3, 157)
-CV_REGISTER(CVRegXMM4, 158)
-CV_REGISTER(CVRegXMM5, 159)
-CV_REGISTER(CVRegXMM6, 160)
-CV_REGISTER(CVRegXMM7, 161)
+CV_REGISTER(MM0, 146)
+CV_REGISTER(MM1, 147)
+CV_REGISTER(MM2, 148)
+CV_REGISTER(MM3, 149)
+CV_REGISTER(MM4, 150)
+CV_REGISTER(MM5, 151)
+CV_REGISTER(MM6, 152)
+CV_REGISTER(MM7, 153)
 
-CV_REGISTER(CVRegMXCSR, 211)
+CV_REGISTER(XMM0, 154)
+CV_REGISTER(XMM1, 155)
+CV_REGISTER(XMM2, 156)
+CV_REGISTER(XMM3, 157)
+CV_REGISTER(XMM4, 158)
+CV_REGISTER(XMM5, 159)
+CV_REGISTER(XMM6, 160)
+CV_REGISTER(XMM7, 161)
 
-CV_REGISTER(CVRegEDXEAX, 212)
+CV_REGISTER(MXCSR, 211)
 
-CV_REGISTER(CVRegEMM0L, 220)
-CV_REGISTER(CVRegEMM1L, 221)
-CV_REGISTER(CVRegEMM2L, 222)
-CV_REGISTER(CVRegEMM3L, 223)
-CV_REGISTER(CVRegEMM4L, 224)
-CV_REGISTER(CVRegEMM5L, 225)
-CV_REGISTER(CVRegEMM6L, 226)
-CV_REGISTER(CVRegEMM7L, 227)
+CV_REGISTER(EDXEAX, 212)
 
-CV_REGISTER(CVRegEMM0H, 228)
-CV_REGISTER(CVRegEMM1H, 229)
-CV_REGISTER(CVRegEMM2H, 230)
-CV_REGISTER(CVRegEMM3H, 231)
-CV_REGISTER(CVRegEMM4H, 232)
-CV_REGISTER(CVRegEMM5H, 233)
-CV_REGISTER(CVRegEMM6H, 234)
-CV_REGISTER(CVRegEMM7H, 235)
+CV_REGISTER(EMM0L, 220)
+CV_REGISTER(EMM1L, 221)
+CV_REGISTER(EMM2L, 222)
+CV_REGISTER(EMM3L, 223)
+CV_REGISTER(EMM4L, 224)
+CV_REGISTER(EMM5L, 225)
+CV_REGISTER(EMM6L, 226)
+CV_REGISTER(EMM7L, 227)
 
-CV_REGISTER(CVRegMM00, 236)
-CV_REGISTER(CVRegMM01, 237)
-CV_REGISTER(CVRegMM10, 238)
-CV_REGISTER(CVRegMM11, 239)
-CV_REGISTER(CVRegMM20, 240)
-CV_REGISTER(CVRegMM21, 241)
-CV_REGISTER(CVRegMM30, 242)
-CV_REGISTER(CVRegMM31, 243)
-CV_REGISTER(CVRegMM40, 244)
-CV_REGISTER(CVRegMM41, 245)
-CV_REGISTER(CVRegMM50, 246)
-CV_REGISTER(CVRegMM51, 247)
-CV_REGISTER(CVRegMM60, 248)
-CV_REGISTER(CVRegMM61, 249)
-CV_REGISTER(CVRegMM70, 250)
-CV_REGISTER(CVRegMM71, 251)
+CV_REGISTER(EMM0H, 228)
+CV_REGISTER(EMM1H, 229)
+CV_REGISTER(EMM2H, 230)
+CV_REGISTER(EMM3H, 231)
+CV_REGISTER(EMM4H, 232)
+CV_REGISTER(EMM5H, 233)
+CV_REGISTER(EMM6H, 234)
+CV_REGISTER(EMM7H, 235)
 
-CV_REGISTER(CVRegBND0, 396)
-CV_REGISTER(CVRegBND1, 397)
-CV_REGISTER(CVRegBND2, 398)
+CV_REGISTER(MM00, 236)
+CV_REGISTER(MM01, 237)
+CV_REGISTER(MM10, 238)
+CV_REGISTER(MM11, 239)
+CV_REGISTER(MM20, 240)
+CV_REGISTER(MM21, 241)
+CV_REGISTER(MM30, 242)
+CV_REGISTER(MM31, 243)
+CV_REGISTER(MM40, 244)
+CV_REGISTER(MM41, 245)
+CV_REGISTER(MM50, 246)
+CV_REGISTER(MM51, 247)
+CV_REGISTER(MM60, 248)
+CV_REGISTER(MM61, 249)
+CV_REGISTER(MM70, 250)
+CV_REGISTER(MM71, 251)
 
+CV_REGISTER(BND0, 396)
+CV_REGISTER(BND1, 397)
+CV_REGISTER(BND2, 398)
 
-CV_REGISTER(CVRegXMM8, 252)
-CV_REGISTER(CVRegXMM9, 253)
-CV_REGISTER(CVRegXMM10, 254)
-CV_REGISTER(CVRegXMM11, 255)
-CV_REGISTER(CVRegXMM12, 256)
-CV_REGISTER(CVRegXMM13, 257)
-CV_REGISTER(CVRegXMM14, 258)
-CV_REGISTER(CVRegXMM15, 259)
 
+CV_REGISTER(XMM8, 252)
+CV_REGISTER(XMM9, 253)
+CV_REGISTER(XMM10, 254)
+CV_REGISTER(XMM11, 255)
+CV_REGISTER(XMM12, 256)
+CV_REGISTER(XMM13, 257)
+CV_REGISTER(XMM14, 258)
+CV_REGISTER(XMM15, 259)
 
-CV_REGISTER(CVRegSIL, 324)
-CV_REGISTER(CVRegDIL, 325)
-CV_REGISTER(CVRegBPL, 326)
-CV_REGISTER(CVRegSPL, 327)
 
-CV_REGISTER(CVRegRAX, 328)
-CV_REGISTER(CVRegRBX, 329)
-CV_REGISTER(CVRegRCX, 330)
-CV_REGISTER(CVRegRDX, 331)
-CV_REGISTER(CVRegRSI, 332)
-CV_REGISTER(CVRegRDI, 333)
-CV_REGISTER(CVRegRBP, 334)
-CV_REGISTER(CVRegRSP, 335)
+CV_REGISTER(SIL, 324)
+CV_REGISTER(DIL, 325)
+CV_REGISTER(BPL, 326)
+CV_REGISTER(SPL, 327)
 
-CV_REGISTER(CVRegR8, 336)
-CV_REGISTER(CVRegR9, 337)
-CV_REGISTER(CVRegR10, 338)
-CV_REGISTER(CVRegR11, 339)
-CV_REGISTER(CVRegR12, 340)
-CV_REGISTER(CVRegR13, 341)
-CV_REGISTER(CVRegR14, 342)
-CV_REGISTER(CVRegR15, 343)
+CV_REGISTER(RAX, 328)
+CV_REGISTER(RBX, 329)
+CV_REGISTER(RCX, 330)
+CV_REGISTER(RDX, 331)
+CV_REGISTER(RSI, 332)
+CV_REGISTER(RDI, 333)
+CV_REGISTER(RBP, 334)
+CV_REGISTER(RSP, 335)
 
-CV_REGISTER(CVRegR8B, 344)
-CV_REGISTER(CVRegR9B, 345)
-CV_REGISTER(CVRegR10B, 346)
-CV_REGISTER(CVRegR11B, 347)
-CV_REGISTER(CVRegR12B, 348)
-CV_REGISTER(CVRegR13B, 349)
-CV_REGISTER(CVRegR14B, 350)
-CV_REGISTER(CVRegR15B, 351)
+CV_REGISTER(R8, 336)
+CV_REGISTER(R9, 337)
+CV_REGISTER(R10, 338)
+CV_REGISTER(R11, 339)
+CV_REGISTER(R12, 340)
+CV_REGISTER(R13, 341)
+CV_REGISTER(R14, 342)
+CV_REGISTER(R15, 343)
 
-CV_REGISTER(CVRegR8W, 352)
-CV_REGISTER(CVRegR9W, 353)
-CV_REGISTER(CVRegR10W, 354)
-CV_REGISTER(CVRegR11W, 355)
-CV_REGISTER(CVRegR12W, 356)
-CV_REGISTER(CVRegR13W, 357)
-CV_REGISTER(CVRegR14W, 358)
-CV_REGISTER(CVRegR15W, 359)
+CV_REGISTER(R8B, 344)
+CV_REGISTER(R9B, 345)
+CV_REGISTER(R10B, 346)
+CV_REGISTER(R11B, 347)
+CV_REGISTER(R12B, 348)
+CV_REGISTER(R13B, 349)
+CV_REGISTER(R14B, 350)
+CV_REGISTER(R15B, 351)
 
-CV_REGISTER(CVRegR8D, 360)
-CV_REGISTER(CVRegR9D, 361)
-CV_REGISTER(CVRegR10D, 362)
-CV_REGISTER(CVRegR11D, 363)
-CV_REGISTER(CVRegR12D, 364)
-CV_REGISTER(CVRegR13D, 365)
-CV_REGISTER(CVRegR14D, 366)
-CV_REGISTER(CVRegR15D, 367)
+CV_REGISTER(R8W, 352)
+CV_REGISTER(R9W, 353)
+CV_REGISTER(R10W, 354)
+CV_REGISTER(R11W, 355)
+CV_REGISTER(R12W, 356)
+CV_REGISTER(R13W, 357)
+CV_REGISTER(R14W, 358)
+CV_REGISTER(R15W, 359)
+
+CV_REGISTER(R8D, 360)
+CV_REGISTER(R9D, 361)
+CV_REGISTER(R10D, 362)
+CV_REGISTER(R11D, 363)
+CV_REGISTER(R12D, 364)
+CV_REGISTER(R13D, 365)
+CV_REGISTER(R14D, 366)
+CV_REGISTER(R15D, 367)
 
 
 // cvconst.h defines both CV_REG_YMM0 (252) and CV_AMD64_YMM0 (368). Keep the
 // original prefix to distinguish them.
 
-CV_REGISTER(CVRegAMD64_YMM0, 368)
-CV_REGISTER(CVRegAMD64_YMM1, 369)
-CV_REGISTER(CVRegAMD64_YMM2, 370)
-CV_REGISTER(CVRegAMD64_YMM3, 371)
-CV_REGISTER(CVRegAMD64_YMM4, 372)
-CV_REGISTER(CVRegAMD64_YMM5, 373)
-CV_REGISTER(CVRegAMD64_YMM6, 374)
-CV_REGISTER(CVRegAMD64_YMM7, 375)
-CV_REGISTER(CVRegAMD64_YMM8, 376)
-CV_REGISTER(CVRegAMD64_YMM9, 377)
-CV_REGISTER(CVRegAMD64_YMM10, 378)
-CV_REGISTER(CVRegAMD64_YMM11, 379)
-CV_REGISTER(CVRegAMD64_YMM12, 380)
-CV_REGISTER(CVRegAMD64_YMM13, 381)
-CV_REGISTER(CVRegAMD64_YMM14, 382)
-CV_REGISTER(CVRegAMD64_YMM15, 383)
+CV_REGISTER(AMD64_YMM0, 368)
+CV_REGISTER(AMD64_YMM1, 369)
+CV_REGISTER(AMD64_YMM2, 370)
+CV_REGISTER(AMD64_YMM3, 371)
+CV_REGISTER(AMD64_YMM4, 372)
+CV_REGISTER(AMD64_YMM5, 373)
+CV_REGISTER(AMD64_YMM6, 374)
+CV_REGISTER(AMD64_YMM7, 375)
+CV_REGISTER(AMD64_YMM8, 376)
+CV_REGISTER(AMD64_YMM9, 377)
+CV_REGISTER(AMD64_YMM10, 378)
+CV_REGISTER(AMD64_YMM11, 379)
+CV_REGISTER(AMD64_YMM12, 380)
+CV_REGISTER(AMD64_YMM13, 381)
+CV_REGISTER(AMD64_YMM14, 382)
+CV_REGISTER(AMD64_YMM15, 383)
+
+CV_REGISTER(AMD64_YMM16, 710)
+CV_REGISTER(AMD64_YMM17, 711)
+CV_REGISTER(AMD64_YMM18, 712)
+CV_REGISTER(AMD64_YMM19, 713)
+CV_REGISTER(AMD64_YMM20, 714)
+CV_REGISTER(AMD64_YMM21, 715)
+CV_REGISTER(AMD64_YMM22, 716)
+CV_REGISTER(AMD64_YMM23, 717)
+CV_REGISTER(AMD64_YMM24, 718)
+CV_REGISTER(AMD64_YMM25, 719)
+CV_REGISTER(AMD64_YMM26, 720)
+CV_REGISTER(AMD64_YMM27, 721)
+CV_REGISTER(AMD64_YMM28, 722)
+CV_REGISTER(AMD64_YMM29, 723)
+CV_REGISTER(AMD64_YMM30, 724)
+CV_REGISTER(AMD64_YMM31, 725)
 
-CV_REGISTER(CVRegAMD64_YMM16, 710)
-CV_REGISTER(CVRegAMD64_YMM17, 711)
-CV_REGISTER(CVRegAMD64_YMM18, 712)
-CV_REGISTER(CVRegAMD64_YMM19, 713)
-CV_REGISTER(CVRegAMD64_YMM20, 714)
-CV_REGISTER(CVRegAMD64_YMM21, 715)
-CV_REGISTER(CVRegAMD64_YMM22, 716)
-CV_REGISTER(CVRegAMD64_YMM23, 717)
-CV_REGISTER(CVRegAMD64_YMM24, 718)
-CV_REGISTER(CVRegAMD64_YMM25, 719)
-CV_REGISTER(CVRegAMD64_YMM26, 720)
-CV_REGISTER(CVRegAMD64_YMM27, 721)
-CV_REGISTER(CVRegAMD64_YMM28, 722)
-CV_REGISTER(CVRegAMD64_YMM29, 723)
-CV_REGISTER(CVRegAMD64_YMM30, 724)
-CV_REGISTER(CVRegAMD64_YMM31, 725)
+CV_REGISTER(AMD64_ZMM0, 726)
+CV_REGISTER(AMD64_ZMM1, 727)
+CV_REGISTER(AMD64_ZMM2, 728)
+CV_REGISTER(AMD64_ZMM3, 729)
+CV_REGISTER(AMD64_ZMM4, 730)
+CV_REGISTER(AMD64_ZMM5, 731)
+CV_REGISTER(AMD64_ZMM6, 732)
+CV_REGISTER(AMD64_ZMM7, 733)
+CV_REGISTER(AMD64_ZMM8, 734)
+CV_REGISTER(AMD64_ZMM9, 735)
+CV_REGISTER(AMD64_ZMM10, 736)
+CV_REGISTER(AMD64_ZMM11, 737)
+CV_REGISTER(AMD64_ZMM12, 738)
+CV_REGISTER(AMD64_ZMM13, 739)
+CV_REGISTER(AMD64_ZMM14, 740)
+CV_REGISTER(AMD64_ZMM15, 741)
+CV_REGISTER(AMD64_ZMM16, 742)
+CV_REGISTER(AMD64_ZMM17, 743)
+CV_REGISTER(AMD64_ZMM18, 744)
+CV_REGISTER(AMD64_ZMM19, 745)
+CV_REGISTER(AMD64_ZMM20, 746)
+CV_REGISTER(AMD64_ZMM21, 747)
+CV_REGISTER(AMD64_ZMM22, 748)
+CV_REGISTER(AMD64_ZMM23, 749)
+CV_REGISTER(AMD64_ZMM24, 750)
+CV_REGISTER(AMD64_ZMM25, 751)
+CV_REGISTER(AMD64_ZMM26, 752)
+CV_REGISTER(AMD64_ZMM27, 753)
+CV_REGISTER(AMD64_ZMM28, 754)
+CV_REGISTER(AMD64_ZMM29, 755)
+CV_REGISTER(AMD64_ZMM30, 756)
+CV_REGISTER(AMD64_ZMM31, 757)
 
-CV_REGISTER(CVRegAMD64_ZMM0, 726)
-CV_REGISTER(CVRegAMD64_ZMM1, 727)
-CV_REGISTER(CVRegAMD64_ZMM2, 728)
-CV_REGISTER(CVRegAMD64_ZMM3, 729)
-CV_REGISTER(CVRegAMD64_ZMM4, 730)
-CV_REGISTER(CVRegAMD64_ZMM5, 731)
-CV_REGISTER(CVRegAMD64_ZMM6, 732)
-CV_REGISTER(CVRegAMD64_ZMM7, 733)
-CV_REGISTER(CVRegAMD64_ZMM8, 734)
-CV_REGISTER(CVRegAMD64_ZMM9, 735)
-CV_REGISTER(CVRegAMD64_ZMM10, 736)
-CV_REGISTER(CVRegAMD64_ZMM11, 737)
-CV_REGISTER(CVRegAMD64_ZMM12, 738)
-CV_REGISTER(CVRegAMD64_ZMM13, 739)
-CV_REGISTER(CVRegAMD64_ZMM14, 740)
-CV_REGISTER(CVRegAMD64_ZMM15, 741)
-CV_REGISTER(CVRegAMD64_ZMM16, 742)
-CV_REGISTER(CVRegAMD64_ZMM17, 743)
-CV_REGISTER(CVRegAMD64_ZMM18, 744)
-CV_REGISTER(CVRegAMD64_ZMM19, 745)
-CV_REGISTER(CVRegAMD64_ZMM20, 746)
-CV_REGISTER(CVRegAMD64_ZMM21, 747)
-CV_REGISTER(CVRegAMD64_ZMM22, 748)
-CV_REGISTER(CVRegAMD64_ZMM23, 749)
-CV_REGISTER(CVRegAMD64_ZMM24, 750)
-CV_REGISTER(CVRegAMD64_ZMM25, 751)
-CV_REGISTER(CVRegAMD64_ZMM26, 752)
-CV_REGISTER(CVRegAMD64_ZMM27, 753)
-CV_REGISTER(CVRegAMD64_ZMM28, 754)
-CV_REGISTER(CVRegAMD64_ZMM29, 755)
-CV_REGISTER(CVRegAMD64_ZMM30, 756)
-CV_REGISTER(CVRegAMD64_ZMM31, 757)
+CV_REGISTER(AMD64_K0, 758)
+CV_REGISTER(AMD64_K1, 759)
+CV_REGISTER(AMD64_K2, 760)
+CV_REGISTER(AMD64_K3, 761)
+CV_REGISTER(AMD64_K4, 762)
+CV_REGISTER(AMD64_K5, 763)
+CV_REGISTER(AMD64_K6, 764)
+CV_REGISTER(AMD64_K7, 765)
 
-CV_REGISTER(CVRegAMD64_K0, 758)
-CV_REGISTER(CVRegAMD64_K1, 759)
-CV_REGISTER(CVRegAMD64_K2, 760)
-CV_REGISTER(CVRegAMD64_K3, 761)
-CV_REGISTER(CVRegAMD64_K4, 762)
-CV_REGISTER(CVRegAMD64_K5, 763)
-CV_REGISTER(CVRegAMD64_K6, 764)
-CV_REGISTER(CVRegAMD64_K7, 765)
+#pragma pop_macro("CR0")
+#pragma pop_macro("CR1")
+#pragma pop_macro("CR2")
+#pragma pop_macro("CR3")
+#pragma pop_macro("CR4")

diff --git a/llvm/lib/DebugInfo/PDB/Native/NativeRawSymbol.cpp b/llvm/lib/DebugInfo/PDB/Native/NativeRawSymbol.cpp
index a4b0295..fbe3348 100644 (file)
--- a/llvm/lib/DebugInfo/PDB/Native/NativeRawSymbol.cpp
+++ b/llvm/lib/DebugInfo/PDB/Native/NativeRawSymbol.cpp
@@ -188,7 +188,7 @@ uint32_t NativeRawSymbol::getLiveRangeStartRelativeVirtualAddress() const {
 }
 
 codeview::RegisterId NativeRawSymbol::getLocalBasePointerRegisterId() const {
-  return codeview::RegisterId::CVRegEAX;
+  return codeview::RegisterId::EAX;
 }
 
 uint32_t NativeRawSymbol::getLowerBoundId() const {
@@ -248,7 +248,7 @@ uint32_t NativeRawSymbol::getRank() const {
 }
 
 codeview::RegisterId NativeRawSymbol::getRegisterId() const {
-  return codeview::RegisterId::CVRegEAX;
+  return codeview::RegisterId::EAX;
 }
 
 uint32_t NativeRawSymbol::getRegisterType() const {

diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
index 99590c5..355b90b 100644 (file)
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
@@ -81,176 +81,176 @@ void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) {
     codeview::RegisterId CVReg;
     MCPhysReg Reg;
   } RegMap[] = {
-      {codeview::RegisterId::CVRegAL, X86::AL},
-      {codeview::RegisterId::CVRegCL, X86::CL},
-      {codeview::RegisterId::CVRegDL, X86::DL},
-      {codeview::RegisterId::CVRegBL, X86::BL},
-      {codeview::RegisterId::CVRegAH, X86::AH},
-      {codeview::RegisterId::CVRegCH, X86::CH},
-      {codeview::RegisterId::CVRegDH, X86::DH},
-      {codeview::RegisterId::CVRegBH, X86::BH},
-      {codeview::RegisterId::CVRegAX, X86::AX},
-      {codeview::RegisterId::CVRegCX, X86::CX},
-      {codeview::RegisterId::CVRegDX, X86::DX},
-      {codeview::RegisterId::CVRegBX, X86::BX},
-      {codeview::RegisterId::CVRegSP, X86::SP},
-      {codeview::RegisterId::CVRegBP, X86::BP},
-      {codeview::RegisterId::CVRegSI, X86::SI},
-      {codeview::RegisterId::CVRegDI, X86::DI},
-      {codeview::RegisterId::CVRegEAX, X86::EAX},
-      {codeview::RegisterId::CVRegECX, X86::ECX},
-      {codeview::RegisterId::CVRegEDX, X86::EDX},
-      {codeview::RegisterId::CVRegEBX, X86::EBX},
-      {codeview::RegisterId::CVRegESP, X86::ESP},
-      {codeview::RegisterId::CVRegEBP, X86::EBP},
-      {codeview::RegisterId::CVRegESI, X86::ESI},
-      {codeview::RegisterId::CVRegEDI, X86::EDI},
-
-      {codeview::RegisterId::CVRegEFLAGS, X86::EFLAGS},
-
-      {codeview::RegisterId::CVRegST0, X86::FP0},
-      {codeview::RegisterId::CVRegST1, X86::FP1},
-      {codeview::RegisterId::CVRegST2, X86::FP2},
-      {codeview::RegisterId::CVRegST3, X86::FP3},
-      {codeview::RegisterId::CVRegST4, X86::FP4},
-      {codeview::RegisterId::CVRegST5, X86::FP5},
-      {codeview::RegisterId::CVRegST6, X86::FP6},
-      {codeview::RegisterId::CVRegST7, X86::FP7},
-
-      {codeview::RegisterId::CVRegXMM0, X86::XMM0},
-      {codeview::RegisterId::CVRegXMM1, X86::XMM1},
-      {codeview::RegisterId::CVRegXMM2, X86::XMM2},
-      {codeview::RegisterId::CVRegXMM3, X86::XMM3},
-      {codeview::RegisterId::CVRegXMM4, X86::XMM4},
-      {codeview::RegisterId::CVRegXMM5, X86::XMM5},
-      {codeview::RegisterId::CVRegXMM6, X86::XMM6},
-      {codeview::RegisterId::CVRegXMM7, X86::XMM7},
-
-      {codeview::RegisterId::CVRegXMM8, X86::XMM8},
-      {codeview::RegisterId::CVRegXMM9, X86::XMM9},
-      {codeview::RegisterId::CVRegXMM10, X86::XMM10},
-      {codeview::RegisterId::CVRegXMM11, X86::XMM11},
-      {codeview::RegisterId::CVRegXMM12, X86::XMM12},
-      {codeview::RegisterId::CVRegXMM13, X86::XMM13},
-      {codeview::RegisterId::CVRegXMM14, X86::XMM14},
-      {codeview::RegisterId::CVRegXMM15, X86::XMM15},
-
-      {codeview::RegisterId::CVRegSIL, X86::SIL},
-      {codeview::RegisterId::CVRegDIL, X86::DIL},
-      {codeview::RegisterId::CVRegBPL, X86::BPL},
-      {codeview::RegisterId::CVRegSPL, X86::SPL},
-      {codeview::RegisterId::CVRegRAX, X86::RAX},
-      {codeview::RegisterId::CVRegRBX, X86::RBX},
-      {codeview::RegisterId::CVRegRCX, X86::RCX},
-      {codeview::RegisterId::CVRegRDX, X86::RDX},
-      {codeview::RegisterId::CVRegRSI, X86::RSI},
-      {codeview::RegisterId::CVRegRDI, X86::RDI},
-      {codeview::RegisterId::CVRegRBP, X86::RBP},
-      {codeview::RegisterId::CVRegRSP, X86::RSP},
-      {codeview::RegisterId::CVRegR8, X86::R8},
-      {codeview::RegisterId::CVRegR9, X86::R9},
-      {codeview::RegisterId::CVRegR10, X86::R10},
-      {codeview::RegisterId::CVRegR11, X86::R11},
-      {codeview::RegisterId::CVRegR12, X86::R12},
-      {codeview::RegisterId::CVRegR13, X86::R13},
-      {codeview::RegisterId::CVRegR14, X86::R14},
-      {codeview::RegisterId::CVRegR15, X86::R15},
-      {codeview::RegisterId::CVRegR8B, X86::R8B},
-      {codeview::RegisterId::CVRegR9B, X86::R9B},
-      {codeview::RegisterId::CVRegR10B, X86::R10B},
-      {codeview::RegisterId::CVRegR11B, X86::R11B},
-      {codeview::RegisterId::CVRegR12B, X86::R12B},
-      {codeview::RegisterId::CVRegR13B, X86::R13B},
-      {codeview::RegisterId::CVRegR14B, X86::R14B},
-      {codeview::RegisterId::CVRegR15B, X86::R15B},
-      {codeview::RegisterId::CVRegR8W, X86::R8W},
-      {codeview::RegisterId::CVRegR9W, X86::R9W},
-      {codeview::RegisterId::CVRegR10W, X86::R10W},
-      {codeview::RegisterId::CVRegR11W, X86::R11W},
-      {codeview::RegisterId::CVRegR12W, X86::R12W},
-      {codeview::RegisterId::CVRegR13W, X86::R13W},
-      {codeview::RegisterId::CVRegR14W, X86::R14W},
-      {codeview::RegisterId::CVRegR15W, X86::R15W},
-      {codeview::RegisterId::CVRegR8D, X86::R8D},
-      {codeview::RegisterId::CVRegR9D, X86::R9D},
-      {codeview::RegisterId::CVRegR10D, X86::R10D},
-      {codeview::RegisterId::CVRegR11D, X86::R11D},
-      {codeview::RegisterId::CVRegR12D, X86::R12D},
-      {codeview::RegisterId::CVRegR13D, X86::R13D},
-      {codeview::RegisterId::CVRegR14D, X86::R14D},
-      {codeview::RegisterId::CVRegR15D, X86::R15D},
-      {codeview::RegisterId::CVRegAMD64_YMM0, X86::YMM0},
-      {codeview::RegisterId::CVRegAMD64_YMM1, X86::YMM1},
-      {codeview::RegisterId::CVRegAMD64_YMM2, X86::YMM2},
-      {codeview::RegisterId::CVRegAMD64_YMM3, X86::YMM3},
-      {codeview::RegisterId::CVRegAMD64_YMM4, X86::YMM4},
-      {codeview::RegisterId::CVRegAMD64_YMM5, X86::YMM5},
-      {codeview::RegisterId::CVRegAMD64_YMM6, X86::YMM6},
-      {codeview::RegisterId::CVRegAMD64_YMM7, X86::YMM7},
-      {codeview::RegisterId::CVRegAMD64_YMM8, X86::YMM8},
-      {codeview::RegisterId::CVRegAMD64_YMM9, X86::YMM9},
-      {codeview::RegisterId::CVRegAMD64_YMM10, X86::YMM10},
-      {codeview::RegisterId::CVRegAMD64_YMM11, X86::YMM11},
-      {codeview::RegisterId::CVRegAMD64_YMM12, X86::YMM12},
-      {codeview::RegisterId::CVRegAMD64_YMM13, X86::YMM13},
-      {codeview::RegisterId::CVRegAMD64_YMM14, X86::YMM14},
-      {codeview::RegisterId::CVRegAMD64_YMM15, X86::YMM15},
-      {codeview::RegisterId::CVRegAMD64_YMM16, X86::YMM16},
-      {codeview::RegisterId::CVRegAMD64_YMM17, X86::YMM17},
-      {codeview::RegisterId::CVRegAMD64_YMM18, X86::YMM18},
-      {codeview::RegisterId::CVRegAMD64_YMM19, X86::YMM19},
-      {codeview::RegisterId::CVRegAMD64_YMM20, X86::YMM20},
-      {codeview::RegisterId::CVRegAMD64_YMM21, X86::YMM21},
-      {codeview::RegisterId::CVRegAMD64_YMM22, X86::YMM22},
-      {codeview::RegisterId::CVRegAMD64_YMM23, X86::YMM23},
-      {codeview::RegisterId::CVRegAMD64_YMM24, X86::YMM24},
-      {codeview::RegisterId::CVRegAMD64_YMM25, X86::YMM25},
-      {codeview::RegisterId::CVRegAMD64_YMM26, X86::YMM26},
-      {codeview::RegisterId::CVRegAMD64_YMM27, X86::YMM27},
-      {codeview::RegisterId::CVRegAMD64_YMM28, X86::YMM28},
-      {codeview::RegisterId::CVRegAMD64_YMM29, X86::YMM29},
-      {codeview::RegisterId::CVRegAMD64_YMM30, X86::YMM30},
-      {codeview::RegisterId::CVRegAMD64_YMM31, X86::YMM31},
-      {codeview::RegisterId::CVRegAMD64_ZMM0, X86::ZMM0},
-      {codeview::RegisterId::CVRegAMD64_ZMM1, X86::ZMM1},
-      {codeview::RegisterId::CVRegAMD64_ZMM2, X86::ZMM2},
-      {codeview::RegisterId::CVRegAMD64_ZMM3, X86::ZMM3},
-      {codeview::RegisterId::CVRegAMD64_ZMM4, X86::ZMM4},
-      {codeview::RegisterId::CVRegAMD64_ZMM5, X86::ZMM5},
-      {codeview::RegisterId::CVRegAMD64_ZMM6, X86::ZMM6},
-      {codeview::RegisterId::CVRegAMD64_ZMM7, X86::ZMM7},
-      {codeview::RegisterId::CVRegAMD64_ZMM8, X86::ZMM8},
-      {codeview::RegisterId::CVRegAMD64_ZMM9, X86::ZMM9},
-      {codeview::RegisterId::CVRegAMD64_ZMM10, X86::ZMM10},
-      {codeview::RegisterId::CVRegAMD64_ZMM11, X86::ZMM11},
-      {codeview::RegisterId::CVRegAMD64_ZMM12, X86::ZMM12},
-      {codeview::RegisterId::CVRegAMD64_ZMM13, X86::ZMM13},
-      {codeview::RegisterId::CVRegAMD64_ZMM14, X86::ZMM14},
-      {codeview::RegisterId::CVRegAMD64_ZMM15, X86::ZMM15},
-      {codeview::RegisterId::CVRegAMD64_ZMM16, X86::ZMM16},
-      {codeview::RegisterId::CVRegAMD64_ZMM17, X86::ZMM17},
-      {codeview::RegisterId::CVRegAMD64_ZMM18, X86::ZMM18},
-      {codeview::RegisterId::CVRegAMD64_ZMM19, X86::ZMM19},
-      {codeview::RegisterId::CVRegAMD64_ZMM20, X86::ZMM20},
-      {codeview::RegisterId::CVRegAMD64_ZMM21, X86::ZMM21},
-      {codeview::RegisterId::CVRegAMD64_ZMM22, X86::ZMM22},
-      {codeview::RegisterId::CVRegAMD64_ZMM23, X86::ZMM23},
-      {codeview::RegisterId::CVRegAMD64_ZMM24, X86::ZMM24},
-      {codeview::RegisterId::CVRegAMD64_ZMM25, X86::ZMM25},
-      {codeview::RegisterId::CVRegAMD64_ZMM26, X86::ZMM26},
-      {codeview::RegisterId::CVRegAMD64_ZMM27, X86::ZMM27},
-      {codeview::RegisterId::CVRegAMD64_ZMM28, X86::ZMM28},
-      {codeview::RegisterId::CVRegAMD64_ZMM29, X86::ZMM29},
-      {codeview::RegisterId::CVRegAMD64_ZMM30, X86::ZMM30},
-      {codeview::RegisterId::CVRegAMD64_ZMM31, X86::ZMM31},
-      {codeview::RegisterId::CVRegAMD64_K0, X86::K0},
-      {codeview::RegisterId::CVRegAMD64_K1, X86::K1},
-      {codeview::RegisterId::CVRegAMD64_K2, X86::K2},
-      {codeview::RegisterId::CVRegAMD64_K3, X86::K3},
-      {codeview::RegisterId::CVRegAMD64_K4, X86::K4},
-      {codeview::RegisterId::CVRegAMD64_K5, X86::K5},
-      {codeview::RegisterId::CVRegAMD64_K6, X86::K6},
-      {codeview::RegisterId::CVRegAMD64_K7, X86::K7},
+      {codeview::RegisterId::AL, X86::AL},
+      {codeview::RegisterId::CL, X86::CL},
+      {codeview::RegisterId::DL, X86::DL},
+      {codeview::RegisterId::BL, X86::BL},
+      {codeview::RegisterId::AH, X86::AH},
+      {codeview::RegisterId::CH, X86::CH},
+      {codeview::RegisterId::DH, X86::DH},
+      {codeview::RegisterId::BH, X86::BH},
+      {codeview::RegisterId::AX, X86::AX},
+      {codeview::RegisterId::CX, X86::CX},
+      {codeview::RegisterId::DX, X86::DX},
+      {codeview::RegisterId::BX, X86::BX},
+      {codeview::RegisterId::SP, X86::SP},
+      {codeview::RegisterId::BP, X86::BP},
+      {codeview::RegisterId::SI, X86::SI},
+      {codeview::RegisterId::DI, X86::DI},
+      {codeview::RegisterId::EAX, X86::EAX},
+      {codeview::RegisterId::ECX, X86::ECX},
+      {codeview::RegisterId::EDX, X86::EDX},
+      {codeview::RegisterId::EBX, X86::EBX},
+      {codeview::RegisterId::ESP, X86::ESP},
+      {codeview::RegisterId::EBP, X86::EBP},
+      {codeview::RegisterId::ESI, X86::ESI},
+      {codeview::RegisterId::EDI, X86::EDI},
+
+      {codeview::RegisterId::EFLAGS, X86::EFLAGS},
+
+      {codeview::RegisterId::ST0, X86::FP0},
+      {codeview::RegisterId::ST1, X86::FP1},
+      {codeview::RegisterId::ST2, X86::FP2},
+      {codeview::RegisterId::ST3, X86::FP3},
+      {codeview::RegisterId::ST4, X86::FP4},
+      {codeview::RegisterId::ST5, X86::FP5},
+      {codeview::RegisterId::ST6, X86::FP6},
+      {codeview::RegisterId::ST7, X86::FP7},
+
+      {codeview::RegisterId::XMM0, X86::XMM0},
+      {codeview::RegisterId::XMM1, X86::XMM1},
+      {codeview::RegisterId::XMM2, X86::XMM2},
+      {codeview::RegisterId::XMM3, X86::XMM3},
+      {codeview::RegisterId::XMM4, X86::XMM4},
+      {codeview::RegisterId::XMM5, X86::XMM5},
+      {codeview::RegisterId::XMM6, X86::XMM6},
+      {codeview::RegisterId::XMM7, X86::XMM7},
+
+      {codeview::RegisterId::XMM8, X86::XMM8},
+      {codeview::RegisterId::XMM9, X86::XMM9},
+      {codeview::RegisterId::XMM10, X86::XMM10},
+      {codeview::RegisterId::XMM11, X86::XMM11},
+      {codeview::RegisterId::XMM12, X86::XMM12},
+      {codeview::RegisterId::XMM13, X86::XMM13},
+      {codeview::RegisterId::XMM14, X86::XMM14},
+      {codeview::RegisterId::XMM15, X86::XMM15},
+
+      {codeview::RegisterId::SIL, X86::SIL},
+      {codeview::RegisterId::DIL, X86::DIL},
+      {codeview::RegisterId::BPL, X86::BPL},
+      {codeview::RegisterId::SPL, X86::SPL},
+      {codeview::RegisterId::RAX, X86::RAX},
+      {codeview::RegisterId::RBX, X86::RBX},
+      {codeview::RegisterId::RCX, X86::RCX},
+      {codeview::RegisterId::RDX, X86::RDX},
+      {codeview::RegisterId::RSI, X86::RSI},
+      {codeview::RegisterId::RDI, X86::RDI},
+      {codeview::RegisterId::RBP, X86::RBP},
+      {codeview::RegisterId::RSP, X86::RSP},
+      {codeview::RegisterId::R8, X86::R8},
+      {codeview::RegisterId::R9, X86::R9},
+      {codeview::RegisterId::R10, X86::R10},
+      {codeview::RegisterId::R11, X86::R11},
+      {codeview::RegisterId::R12, X86::R12},
+      {codeview::RegisterId::R13, X86::R13},
+      {codeview::RegisterId::R14, X86::R14},
+      {codeview::RegisterId::R15, X86::R15},
+      {codeview::RegisterId::R8B, X86::R8B},
+      {codeview::RegisterId::R9B, X86::R9B},
+      {codeview::RegisterId::R10B, X86::R10B},
+      {codeview::RegisterId::R11B, X86::R11B},
+      {codeview::RegisterId::R12B, X86::R12B},
+      {codeview::RegisterId::R13B, X86::R13B},
+      {codeview::RegisterId::R14B, X86::R14B},
+      {codeview::RegisterId::R15B, X86::R15B},
+      {codeview::RegisterId::R8W, X86::R8W},
+      {codeview::RegisterId::R9W, X86::R9W},
+      {codeview::RegisterId::R10W, X86::R10W},
+      {codeview::RegisterId::R11W, X86::R11W},
+      {codeview::RegisterId::R12W, X86::R12W},
+      {codeview::RegisterId::R13W, X86::R13W},
+      {codeview::RegisterId::R14W, X86::R14W},
+      {codeview::RegisterId::R15W, X86::R15W},
+      {codeview::RegisterId::R8D, X86::R8D},
+      {codeview::RegisterId::R9D, X86::R9D},
+      {codeview::RegisterId::R10D, X86::R10D},
+      {codeview::RegisterId::R11D, X86::R11D},
+      {codeview::RegisterId::R12D, X86::R12D},
+      {codeview::RegisterId::R13D, X86::R13D},
+      {codeview::RegisterId::R14D, X86::R14D},
+      {codeview::RegisterId::R15D, X86::R15D},
+      {codeview::RegisterId::AMD64_YMM0, X86::YMM0},
+      {codeview::RegisterId::AMD64_YMM1, X86::YMM1},
+      {codeview::RegisterId::AMD64_YMM2, X86::YMM2},
+      {codeview::RegisterId::AMD64_YMM3, X86::YMM3},
+      {codeview::RegisterId::AMD64_YMM4, X86::YMM4},
+      {codeview::RegisterId::AMD64_YMM5, X86::YMM5},
+      {codeview::RegisterId::AMD64_YMM6, X86::YMM6},
+      {codeview::RegisterId::AMD64_YMM7, X86::YMM7},
+      {codeview::RegisterId::AMD64_YMM8, X86::YMM8},
+      {codeview::RegisterId::AMD64_YMM9, X86::YMM9},
+      {codeview::RegisterId::AMD64_YMM10, X86::YMM10},
+      {codeview::RegisterId::AMD64_YMM11, X86::YMM11},
+      {codeview::RegisterId::AMD64_YMM12, X86::YMM12},
+      {codeview::RegisterId::AMD64_YMM13, X86::YMM13},
+      {codeview::RegisterId::AMD64_YMM14, X86::YMM14},
+      {codeview::RegisterId::AMD64_YMM15, X86::YMM15},
+      {codeview::RegisterId::AMD64_YMM16, X86::YMM16},
+      {codeview::RegisterId::AMD64_YMM17, X86::YMM17},
+      {codeview::RegisterId::AMD64_YMM18, X86::YMM18},
+      {codeview::RegisterId::AMD64_YMM19, X86::YMM19},
+      {codeview::RegisterId::AMD64_YMM20, X86::YMM20},
+      {codeview::RegisterId::AMD64_YMM21, X86::YMM21},
+      {codeview::RegisterId::AMD64_YMM22, X86::YMM22},
+      {codeview::RegisterId::AMD64_YMM23, X86::YMM23},
+      {codeview::RegisterId::AMD64_YMM24, X86::YMM24},
+      {codeview::RegisterId::AMD64_YMM25, X86::YMM25},
+      {codeview::RegisterId::AMD64_YMM26, X86::YMM26},
+      {codeview::RegisterId::AMD64_YMM27, X86::YMM27},
+      {codeview::RegisterId::AMD64_YMM28, X86::YMM28},
+      {codeview::RegisterId::AMD64_YMM29, X86::YMM29},
+      {codeview::RegisterId::AMD64_YMM30, X86::YMM30},
+      {codeview::RegisterId::AMD64_YMM31, X86::YMM31},
+      {codeview::RegisterId::AMD64_ZMM0, X86::ZMM0},
+      {codeview::RegisterId::AMD64_ZMM1, X86::ZMM1},
+      {codeview::RegisterId::AMD64_ZMM2, X86::ZMM2},
+      {codeview::RegisterId::AMD64_ZMM3, X86::ZMM3},
+      {codeview::RegisterId::AMD64_ZMM4, X86::ZMM4},
+      {codeview::RegisterId::AMD64_ZMM5, X86::ZMM5},
+      {codeview::RegisterId::AMD64_ZMM6, X86::ZMM6},
+      {codeview::RegisterId::AMD64_ZMM7, X86::ZMM7},
+      {codeview::RegisterId::AMD64_ZMM8, X86::ZMM8},
+      {codeview::RegisterId::AMD64_ZMM9, X86::ZMM9},
+      {codeview::RegisterId::AMD64_ZMM10, X86::ZMM10},
+      {codeview::RegisterId::AMD64_ZMM11, X86::ZMM11},
+      {codeview::RegisterId::AMD64_ZMM12, X86::ZMM12},
+      {codeview::RegisterId::AMD64_ZMM13, X86::ZMM13},
+      {codeview::RegisterId::AMD64_ZMM14, X86::ZMM14},
+      {codeview::RegisterId::AMD64_ZMM15, X86::ZMM15},
+      {codeview::RegisterId::AMD64_ZMM16, X86::ZMM16},
+      {codeview::RegisterId::AMD64_ZMM17, X86::ZMM17},
+      {codeview::RegisterId::AMD64_ZMM18, X86::ZMM18},
+      {codeview::RegisterId::AMD64_ZMM19, X86::ZMM19},
+      {codeview::RegisterId::AMD64_ZMM20, X86::ZMM20},
+      {codeview::RegisterId::AMD64_ZMM21, X86::ZMM21},
+      {codeview::RegisterId::AMD64_ZMM22, X86::ZMM22},
+      {codeview::RegisterId::AMD64_ZMM23, X86::ZMM23},
+      {codeview::RegisterId::AMD64_ZMM24, X86::ZMM24},
+      {codeview::RegisterId::AMD64_ZMM25, X86::ZMM25},
+      {codeview::RegisterId::AMD64_ZMM26, X86::ZMM26},
+      {codeview::RegisterId::AMD64_ZMM27, X86::ZMM27},
+      {codeview::RegisterId::AMD64_ZMM28, X86::ZMM28},
+      {codeview::RegisterId::AMD64_ZMM29, X86::ZMM29},
+      {codeview::RegisterId::AMD64_ZMM30, X86::ZMM30},
+      {codeview::RegisterId::AMD64_ZMM31, X86::ZMM31},
+      {codeview::RegisterId::AMD64_K0, X86::K0},
+      {codeview::RegisterId::AMD64_K1, X86::K1},
+      {codeview::RegisterId::AMD64_K2, X86::K2},
+      {codeview::RegisterId::AMD64_K3, X86::K3},
+      {codeview::RegisterId::AMD64_K4, X86::K4},
+      {codeview::RegisterId::AMD64_K5, X86::K5},
+      {codeview::RegisterId::AMD64_K6, X86::K6},
+      {codeview::RegisterId::AMD64_K7, X86::K7},
   };
   for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
     MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));

diff --git a/llvm/test/DebugInfo/COFF/fp-stack.ll b/llvm/test/DebugInfo/COFF/fp-stack.ll
index 65ec9ed..2d57e5a 100644 (file)
--- a/llvm/test/DebugInfo/COFF/fp-stack.ll
+++ b/llvm/test/DebugInfo/COFF/fp-stack.ll
@@ -12,7 +12,7 @@ entry:
 
 ; ASM:         .cv_def_range    Lfunc_begin0 Lfunc_end0, "A\021\200\000\000\000"
 ; OBJ:    DefRangeRegisterSym {
-; OBJ:      Register: CVRegST0 (0x80)
+; OBJ:      Register: ST0 (0x80)
 ; OBJ:      MayHaveNoName: 0
 ; OBJ:      LocalVariableAddrRange {
 ; OBJ:        OffsetStart: .text+0x0

diff --git a/llvm/test/DebugInfo/COFF/local-variable-gap.ll b/llvm/test/DebugInfo/COFF/local-variable-gap.ll
index fcc4dd9..04a3ea9 100644 (file)
--- a/llvm/test/DebugInfo/COFF/local-variable-gap.ll
+++ b/llvm/test/DebugInfo/COFF/local-variable-gap.ll
@@ -73,7 +73,7 @@
 ; OBJ-NOT:     LocalSym {
 ; OBJ:         DefRangeRegisterSym {
 ; OBJ-NEXT:      Kind:
-; OBJ-NEXT:      Register: CVRegESI (0x17)
+; OBJ-NEXT:      Register: ESI (0x17)
 ; OBJ-NEXT:      MayHaveNoName: 0
 ; OBJ-NEXT:      LocalVariableAddrRange {
 ; OBJ-NEXT:        OffsetStart: .text+0x{{.*}}

diff --git a/llvm/test/DebugInfo/COFF/local-variables.ll b/llvm/test/DebugInfo/COFF/local-variables.ll
index 2bd1cbf..be78478 100644 (file)
--- a/llvm/test/DebugInfo/COFF/local-variables.ll
+++ b/llvm/test/DebugInfo/COFF/local-variables.ll
@@ -111,7 +111,7 @@
 ; OBJ:      VarName: param
 ; OBJ:    }
 ; OBJ:    DefRangeRegisterRelSym {
-; OBJ:      BaseRegister: CVRegRSP (0x14F)
+; OBJ:      BaseRegister: RSP (0x14F)
 ; OBJ:      HasSpilledUDTMember: No
 ; OBJ:      OffsetInParent: 0
 ; OBJ:      BasePointerOffset: 52
@@ -128,7 +128,7 @@
 ; OBJ:      VarName: a
 ; OBJ:    }
 ; OBJ:    DefRangeRegisterRelSym {
-; OBJ:      BaseRegister: CVRegRSP (0x14F)
+; OBJ:      BaseRegister: RSP (0x14F)
 ; OBJ:      HasSpilledUDTMember: No
 ; OBJ:      OffsetInParent: 0
 ; OBJ:      BasePointerOffset: 40
@@ -145,7 +145,7 @@
 ; OBJ:      VarName: b
 ; OBJ:    }
 ; OBJ:    DefRangeRegisterRelSym {
-; OBJ:      BaseRegister: CVRegRSP (0x14F)
+; OBJ:      BaseRegister: RSP (0x14F)
 ; OBJ:      HasSpilledUDTMember: No
 ; OBJ:      OffsetInParent: 0
 ; OBJ:      BasePointerOffset: 36
@@ -173,7 +173,7 @@
 ; OBJ:      VarName: v
 ; OBJ:    }
 ; OBJ:    DefRangeRegisterRelSym {
-; OBJ:      BaseRegister: CVRegRSP (0x14F)
+; OBJ:      BaseRegister: RSP (0x14F)
 ; OBJ:      HasSpilledUDTMember: No
 ; OBJ:      OffsetInParent: 0
 ; OBJ:      BasePointerOffset: 44
@@ -203,7 +203,7 @@
 ; OBJ:      VarName: v
 ; OBJ:    }
 ; OBJ:    DefRangeRegisterRelSym {
-; OBJ:      BaseRegister: CVRegRSP (0x14F)
+; OBJ:      BaseRegister: RSP (0x14F)
 ; OBJ:      HasSpilledUDTMember: No
 ; OBJ:      OffsetInParent: 0
 ; OBJ:      BasePointerOffset: 48

diff --git a/llvm/test/DebugInfo/COFF/pieces.ll b/llvm/test/DebugInfo/COFF/pieces.ll
index d6a5370..64f3225 100644 (file)
--- a/llvm/test/DebugInfo/COFF/pieces.ll
+++ b/llvm/test/DebugInfo/COFF/pieces.ll
@@ -116,14 +116,14 @@
 ; OBJ:         VarName: o
 ; OBJ:       }
 ; OBJ:       DefRangeSubfieldRegisterSym {
-; OBJ:         Register: CVRegEDI (0x18)
+; OBJ:         Register: EDI (0x18)
 ; OBJ:         MayHaveNoName: 0
 ; OBJ:         OffsetInParent: 0
 ; OBJ:         LocalVariableAddrRange {
 ; OBJ:         }
 ; OBJ:       }
 ; OBJ:       DefRangeSubfieldRegisterSym {
-; OBJ:         Register: CVRegESI (0x17)
+; OBJ:         Register: ESI (0x17)
 ; OBJ:         MayHaveNoName: 0
 ; OBJ:         OffsetInParent: 4
 ; OBJ:         LocalVariableAddrRange {
@@ -146,7 +146,7 @@
 ; OBJ:         VarName: o
 ; OBJ:       }
 ; OBJ:       DefRangeSubfieldRegisterSym {
-; OBJ:         Register: CVRegECX (0x12)
+; OBJ:         Register: ECX (0x12)
 ; OBJ:         MayHaveNoName: 0
 ; OBJ:         OffsetInParent: 4
 ; OBJ:         LocalVariableAddrRange {
@@ -169,7 +169,7 @@
 ; OBJ:         VarName: o
 ; OBJ:       }
 ; OBJ:       DefRangeSubfieldRegisterSym {
-; OBJ:         Register: CVRegECX (0x12)
+; OBJ:         Register: ECX (0x12)
 ; OBJ:         MayHaveNoName: 0
 ; OBJ:         OffsetInParent: 0
 ; OBJ:         LocalVariableAddrRange {
@@ -196,7 +196,7 @@
 ; OBJ:         VarName: o
 ; OBJ:       }
 ; OBJ:       DefRangeRegisterRelSym {
-; OBJ:         BaseRegister: CVRegRCX (0x14A)
+; OBJ:         BaseRegister: RCX (0x14A)
 ; OBJ:         HasSpilledUDTMember: No
 ; OBJ:         OffsetInParent: 0
 ; OBJ:         BasePointerOffset: 0
@@ -207,7 +207,7 @@
 ; OBJ:         VarName: p
 ; OBJ:       }
 ; OBJ:       DefRangeSubfieldRegisterSym {
-; OBJ:         Register: CVRegEAX (0x11)
+; OBJ:         Register: EAX (0x11)
 ; OBJ:         MayHaveNoName: 0
 ; OBJ:         OffsetInParent: 4
 ; OBJ:         LocalVariableAddrRange {
@@ -231,7 +231,7 @@
 ; OBJ:         VarName: o
 ; OBJ:       }
 ; OBJ:       DefRangeRegisterRelSym {
-; OBJ:         BaseRegister: CVRegRSP (0x14F)
+; OBJ:         BaseRegister: RSP (0x14F)
 ; OBJ:         HasSpilledUDTMember: Yes
 ; OBJ:         OffsetInParent: 4
 ; OBJ:         BasePointerOffset: 36

diff --git a/llvm/test/DebugInfo/COFF/register-variables.ll b/llvm/test/DebugInfo/COFF/register-variables.ll
index 01219c6..24daa3c 100644 (file)
--- a/llvm/test/DebugInfo/COFF/register-variables.ll
+++ b/llvm/test/DebugInfo/COFF/register-variables.ll
@@ -92,7 +92,7 @@
 ; OBJ:     VarName: p
 ; OBJ:   }
 ; OBJ:   DefRangeRegisterSym {
-; OBJ:     Register: CVRegECX (0x12)
+; OBJ:     Register: ECX (0x12)
 ; OBJ:     LocalVariableAddrRange {
 ; OBJ:       OffsetStart: .text+0x0
 ; OBJ:       ISectStart: 0x0
@@ -100,7 +100,7 @@
 ; OBJ:     }
 ; OBJ:   }
 ; OBJ:   DefRangeRegisterSym {
-; OBJ:     Register: CVRegESI (0x17)
+; OBJ:     Register: ESI (0x17)
 ; OBJ:     LocalVariableAddrRange {
 ; OBJ:       OffsetStart: .text+0x7
 ; OBJ:       ISectStart: 0x0
@@ -114,7 +114,7 @@
 ; OBJ:     VarName: c
 ; OBJ:   }
 ; OBJ:   DefRangeRegisterSym {
-; OBJ:     Register: CVRegEAX (0x11)
+; OBJ:     Register: EAX (0x11)
 ; OBJ:     LocalVariableAddrRange {
 ; OBJ:       OffsetStart: .text+0xC
 ; OBJ:       ISectStart: 0x0
@@ -128,7 +128,7 @@
 ; OBJ:     VarName: a
 ; OBJ:   }
 ; OBJ:   DefRangeRegisterSym {
-; OBJ:     Register: CVRegEAX (0x11)
+; OBJ:     Register: EAX (0x11)
 ; OBJ:     LocalVariableAddrRange {
 ; OBJ:       OffsetStart: .text+0xC
 ; OBJ:       ISectStart: 0x0
@@ -142,7 +142,7 @@
 ; OBJ:     VarName: b
 ; OBJ:   }
 ; OBJ:   DefRangeRegisterSym {
-; OBJ:     Register: CVRegEAX (0x11)
+; OBJ:     Register: EAX (0x11)
 ; OBJ:     MayHaveNoName: 0
 ; OBJ:       OffsetStart: .text+0x13
 ; OBJ:       ISectStart: 0x0
@@ -162,7 +162,7 @@
 ; OBJ:     VarName: a
 ; OBJ:   }
 ; OBJ:   DefRangeRegisterSym {
-; OBJ:     Register: CVRegEAX (0x11)
+; OBJ:     Register: EAX (0x11)
 ; OBJ:     LocalVariableAddrRange {
 ; OBJ:       OffsetStart: .text+0xC
 ; OBJ:       ISectStart: 0x0
@@ -176,7 +176,7 @@
 ; OBJ:     VarName: b
 ; OBJ:   }
 ; OBJ:   DefRangeRegisterSym {
-; OBJ:     Register: CVRegEAX (0x11)
+; OBJ:     Register: EAX (0x11)
 ; OBJ:     LocalVariableAddrRange {
 ; OBJ:       OffsetStart: .text+0x13
 ; OBJ:       ISectStart: 0x0

diff --git a/llvm/test/DebugInfo/COFF/types-array.ll b/llvm/test/DebugInfo/COFF/types-array.ll
index d9d6b67..10ae426 100644 (file)
--- a/llvm/test/DebugInfo/COFF/types-array.ll
+++ b/llvm/test/DebugInfo/COFF/types-array.ll
@@ -68,7 +68,7 @@
 ; CHECK:       VarName: a
 ; CHECK:     }
 ; CHECK:     DefRangeRegisterRelSym {
-; CHECK:       BaseRegister: CVRegEBP (0x16)
+; CHECK:       BaseRegister: EBP (0x16)
 ; CHECK:       HasSpilledUDTMember: No
 ; CHECK:       OffsetInParent: 0
 ; CHECK:       BasePointerOffset: -20

diff --git a/llvm/test/DebugInfo/PDB/DIA/pdbdump-symbol-format.test b/llvm/test/DebugInfo/PDB/DIA/pdbdump-symbol-format.test
index 998ec7f..4b247da 100644 (file)
--- a/llvm/test/DebugInfo/PDB/DIA/pdbdump-symbol-format.test
+++ b/llvm/test/DebugInfo/PDB/DIA/pdbdump-symbol-format.test
@@ -14,14 +14,14 @@
 
 ; SYM_FORMAT: ---SYMBOLS---
 ; SYM_FORMAT: symbolformat.obj
-; SYM_FORMAT-DAG: func [{{.*}}] (CVRegEBP) int __cdecl _purecall()
-; SYM_FORMAT-DAG: func [{{.*}}] (CVRegEBP) int __cdecl main(int argc, char** argv)
-; SYM_FORMAT-DAG: func [{{.*}}] (CVRegEBP) void A::A()
-; SYM_FORMAT-DAG: func [{{.*}}] (CVRegEBP) void B::B()
+; SYM_FORMAT-DAG: func [{{.*}}] (EBP) int __cdecl _purecall()
+; SYM_FORMAT-DAG: func [{{.*}}] (EBP) int __cdecl main(int argc, char** argv)
+; SYM_FORMAT-DAG: func [{{.*}}] (EBP) void A::A()
+; SYM_FORMAT-DAG: func [{{.*}}] (EBP) void B::B()
 ; SYM_FORMAT-DAG: thunk [{{.*}}] (Pcode) B::`vcall'{0}'
-; SYM_FORMAT-DAG: func [{{.*}}] (CVRegEBP) virtual void B::PureFunc()
-; SYM_FORMAT-DAG: func [{{.*}}] (CVRegEBP) void A::RegularFunc()
-; SYM_FORMAT-DAG: func [{{.*}}] (CVRegEBP) virtual void A::VirtualFunc()
+; SYM_FORMAT-DAG: func [{{.*}}] (EBP) virtual void B::PureFunc()
+; SYM_FORMAT-DAG: func [{{.*}}] (EBP) void A::RegularFunc()
+; SYM_FORMAT-DAG: func [{{.*}}] (EBP) virtual void A::VirtualFunc()
 
 ; TYPES_FORMAT: ---TYPES---
 ; TYPES_FORMAT: Enums

diff --git a/llvm/test/DebugInfo/X86/dbg-declare-inalloca.ll b/llvm/test/DebugInfo/X86/dbg-declare-inalloca.ll
index 4cb9a5e..a437ecd 100644 (file)
--- a/llvm/test/DebugInfo/X86/dbg-declare-inalloca.ll
+++ b/llvm/test/DebugInfo/X86/dbg-declare-inalloca.ll
@@ -67,7 +67,7 @@
 ; OBJ:   VarName: a
 ; OBJ: }
 ; OBJ: DefRangeRegisterRelSym {
-; OBJ:   BaseRegister: CVRegESP (0x15)
+; OBJ:   BaseRegister: ESP (0x15)
 ; OBJ:   BasePointerOffset: 12
 ; OBJ: }
 ; OBJ: LocalSym {
@@ -78,7 +78,7 @@
 ; OBJ:   VarName: b
 ; OBJ: }
 ; OBJ: DefRangeRegisterRelSym {
-; OBJ:   BaseRegister: CVRegESP (0x15)
+; OBJ:   BaseRegister: ESP (0x15)
 ; OBJ:   BasePointerOffset: 16
 ; OBJ: }
 ; FIXME: Retain unused.
@@ -90,7 +90,7 @@
 ; OBJ:   VarName: c
 ; OBJ: }
 ; OBJ: DefRangeRegisterRelSym {
-; OBJ:   BaseRegister: CVRegESP (0x15)
+; OBJ:   BaseRegister: ESP (0x15)
 ; OBJ:   BasePointerOffset: 24
 ; OBJ: }
 ; OBJ-LABEL: ProcEnd {

diff --git a/llvm/test/MC/COFF/cv-def-range-gap.s b/llvm/test/MC/COFF/cv-def-range-gap.s
index f1735e2..2a1a179 100644 (file)
--- a/llvm/test/MC/COFF/cv-def-range-gap.s
+++ b/llvm/test/MC/COFF/cv-def-range-gap.s
@@ -9,7 +9,7 @@
 # CHECK-NOT:     LocalSym {
 # CHECK:         DefRangeRegisterSym {
 # CHECK-NEXT:      Kind: S_DEFRANGE_REGISTER (0x1141)
-# CHECK-NEXT:      Register: CVRegESI (0x17)
+# CHECK-NEXT:      Register: ESI (0x17)
 # CHECK-NEXT:      MayHaveNoName: 0
 # CHECK-NEXT:      LocalVariableAddrRange {
 # CHECK-NEXT:        OffsetStart: .text+0x5
@@ -23,7 +23,7 @@
 # CHECK-NEXT:    }
 # CHECK-NEXT:    DefRangeRegisterSym {
 # CHECK-NEXT:      Kind: S_DEFRANGE_REGISTER (0x1141)
-# CHECK-NEXT:      Register: CVRegESI (0x17)
+# CHECK-NEXT:      Register: ESI (0x17)
 # CHECK-NEXT:      MayHaveNoName: 0
 # CHECK-NEXT:      LocalVariableAddrRange {
 # CHECK-NEXT:        OffsetStart: .text+0x10015
@@ -33,7 +33,7 @@
 # CHECK-NEXT:    }
 # CHECK-NEXT:    DefRangeRegisterSym {
 # CHECK-NEXT:      Kind: S_DEFRANGE_REGISTER (0x1141)
-# CHECK-NEXT:      Register: CVRegESI (0x17)
+# CHECK-NEXT:      Register: ESI (0x17)
 # CHECK-NEXT:      MayHaveNoName: 0
 # CHECK-NEXT:      LocalVariableAddrRange {
 # CHECK-NEXT:        OffsetStart: .text+0x2001B
@@ -43,7 +43,7 @@
 # CHECK-NEXT:    }
 # CHECK-NEXT:    DefRangeRegisterSym {
 # CHECK-NEXT:      Kind: S_DEFRANGE_REGISTER (0x1141)
-# CHECK-NEXT:      Register: CVRegESI (0x17)
+# CHECK-NEXT:      Register: ESI (0x17)
 # CHECK-NEXT:      MayHaveNoName: 0
 # CHECK-NEXT:      LocalVariableAddrRange {
 # CHECK-NEXT:        OffsetStart: .text+0x2001C

diff --git a/llvm/unittests/DebugInfo/CodeView/TypeIndexDiscoveryTest.cpp b/llvm/unittests/DebugInfo/CodeView/TypeIndexDiscoveryTest.cpp
index 7ee5604..1b89160 100644 (file)
--- a/llvm/unittests/DebugInfo/CodeView/TypeIndexDiscoveryTest.cpp
+++ b/llvm/unittests/DebugInfo/CodeView/TypeIndexDiscoveryTest.cpp
@@ -555,7 +555,7 @@ TEST_F(TypeIndexIteratorTest, DataSym) {
 TEST_F(TypeIndexIteratorTest, RegisterSym) {
   RegisterSym Reg(SymbolRecordKind::RegisterSym);
   Reg.Index = TypeIndex::UInt32();
-  Reg.Register = RegisterId::CVRegEAX;
+  Reg.Register = RegisterId::EAX;
   Reg.Name = "Target";
   writeSymbolRecords(Reg);
   checkTypeReferences(0, Reg.Index);