OMAPDSS: DSI: Fix HSYNC, VSYNC and DE polarities between DISPC and DSI
authorArchit Taneja <archit@ti.com>
Tue, 26 Jun 2012 07:08:31 +0000 (12:38 +0530)
committerTomi Valkeinen <tomi.valkeinen@ti.com>
Fri, 29 Jun 2012 07:15:54 +0000 (10:15 +0300)
For DSI operation in videomode, DISPC logic levels for the signals HSYNC, VSYNC
and DE need to be specified to DSI via the fields VP_HSYNC_POL, VP_VSYNC_POL and
VP_DE_POL in DSI_CTRL registers.

This information is completely internal to DSS as logic levels for the above
signals hold no meaning on the DSI bus. Hence a DSI panel driver should be
totally oblivious of these fields.

Fix the logic levels/polarities in the DISPC and DSI registers to a default
value. This is done by overriding these fields in omap_video_timings struct
filled by the panel driver for DISPC, and use the equivalent default values
when programming DSI_CTRL registers. Also, remove the redundant polarity related
fields in omap_dss_dsi_videomode_data.

Signed-off-by: Archit Taneja <archit@ti.com>
drivers/video/omap2/dss/dsi.c
include/video/omapdss.h

index 06b5780..e0d43b2 100644 (file)
@@ -3631,17 +3631,14 @@ static void dsi_config_vp_num_line_buffers(struct omap_dss_device *dssdev)
 static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev)
 {
        struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
-       int de_pol = dssdev->panel.dsi_vm_data.vp_de_pol;
-       int hsync_pol = dssdev->panel.dsi_vm_data.vp_hsync_pol;
-       int vsync_pol = dssdev->panel.dsi_vm_data.vp_vsync_pol;
        bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end;
        bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
        u32 r;
 
        r = dsi_read_reg(dsidev, DSI_CTRL);
-       r = FLD_MOD(r, de_pol, 9, 9);           /* VP_DE_POL */
-       r = FLD_MOD(r, hsync_pol, 10, 10);      /* VP_HSYNC_POL */
-       r = FLD_MOD(r, vsync_pol, 11, 11);      /* VP_VSYNC_POL */
+       r = FLD_MOD(r, 1, 9, 9);                /* VP_DE_POL */
+       r = FLD_MOD(r, 1, 10, 10);              /* VP_HSYNC_POL */
+       r = FLD_MOD(r, 1, 11, 11);              /* VP_VSYNC_POL */
        r = FLD_MOD(r, 1, 15, 15);              /* VP_VSYNC_START */
        r = FLD_MOD(r, vsync_end, 16, 16);      /* VP_VSYNC_END */
        r = FLD_MOD(r, 1, 17, 17);              /* VP_HSYNC_START */
@@ -4343,22 +4340,22 @@ EXPORT_SYMBOL(omap_dsi_update);
 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
 {
        int r;
+       struct omap_video_timings timings;
 
        if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
                u16 dw, dh;
                u32 irq;
-               struct omap_video_timings timings = {
-                       .hsw            = 1,
-                       .hfp            = 1,
-                       .hbp            = 1,
-                       .vsw            = 1,
-                       .vfp            = 0,
-                       .vbp            = 0,
-               };
 
                dssdev->driver->get_resolution(dssdev, &dw, &dh);
+
                timings.x_res = dw;
                timings.y_res = dh;
+               timings.hsw = 1;
+               timings.hfp = 1;
+               timings.hbp = 1;
+               timings.vsw = 1;
+               timings.vfp = 0;
+               timings.vbp = 0;
 
                irq = dispc_mgr_get_framedone_irq(dssdev->manager->id);
 
@@ -4371,15 +4368,26 @@ static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
 
                dispc_mgr_enable_stallmode(dssdev->manager->id, true);
                dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1);
-
-               dss_mgr_set_timings(dssdev->manager, &timings);
        } else {
+               timings = dssdev->panel.timings;
+
                dispc_mgr_enable_stallmode(dssdev->manager->id, false);
                dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0);
-
-               dss_mgr_set_timings(dssdev->manager, &dssdev->panel.timings);
        }
 
+       /*
+        * override interlace, logic level and edge related parameters in
+        * omap_video_timings with default values
+        */
+       timings.interlace = false;
+       timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
+       timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
+       timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
+       timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
+       timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
+
+       dss_mgr_set_timings(dssdev->manager, &timings);
+
        dispc_mgr_set_lcd_type_tft(dssdev->manager->id);
 
        dispc_mgr_set_tft_data_lines(dssdev->manager->id,
index d8ab944..a6267a2 100644 (file)
@@ -261,9 +261,6 @@ struct omap_dss_dsi_videomode_data {
        int hfp_blanking_mode;
 
        /* Video port sync events */
-       int vp_de_pol;
-       int vp_hsync_pol;
-       int vp_vsync_pol;
        bool vp_vsync_end;
        bool vp_hsync_end;