isl: the display engine requires 64B alignment for linear surfaces

v2: Add PRM quote (Lionel)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 5c34efb..6b9e6c9 100644 (file)
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1519,6 +1519,14 @@ isl_surf_init_s(const struct isl_device *dev,
          }
       }
       base_alignment_B = isl_round_up_to_power_of_two(base_alignment_B);
+
+      /* From the Skylake PRM Vol 2c, PLANE_STRIDE::Stride:
+       *
+       *     "For Linear memory, this field specifies the stride in chunks of
+       *     64 bytes (1 cache line)."
+       */
+      if (isl_surf_usage_is_display(info->usage))
+         base_alignment_B = MAX(base_alignment_B, 64);
    } else {
       const uint32_t total_h_tl =
          isl_align_div(phys_total_el.h, tile_info.logical_extent_el.height);