FIXME: Make this optional later. */
#ifndef TRACE_CASE
-#define TRACE_CASE 1
+#define TRACE_CASE (disdata->trace_case)
#endif
+enum cris_disass_family
+ { cris_dis_v0_v10, cris_dis_common_v10_v32, cris_dis_v32 };
+
+/* Stored in the disasm_info->private_data member. */
+struct cris_disasm_data
+{
+ /* Whether to print something less confusing if we find something
+ matching a switch-construct. */
+ bfd_boolean trace_case;
+
+ /* Whether this code is flagged as crisv32. FIXME: Should be an enum
+ that includes "compatible". */
+ enum cris_disass_family distype;
+};
+
/* Value of first element in switch. */
static long case_offset = 0;
static int number_of_bits
PARAMS ((unsigned int));
static char *format_hex
- PARAMS ((unsigned long, char *));
+ PARAMS ((unsigned long, char *, struct cris_disasm_data *));
static char *format_dec
PARAMS ((long, char *, int));
static char *format_reg
- PARAMS ((int, char *, bfd_boolean));
+ PARAMS ((struct cris_disasm_data *, int, char *, bfd_boolean));
+static char *format_sup_reg
+ PARAMS ((unsigned int, char *, bfd_boolean));
static int cris_constraint
- PARAMS ((const char *, unsigned int, unsigned int));
+ PARAMS ((const char *, unsigned int, unsigned int,
+ struct cris_disasm_data *));
static unsigned bytes_to_skip
- PARAMS ((unsigned int, const struct cris_opcode *));
+ PARAMS ((unsigned int, const struct cris_opcode *,
+ enum cris_disass_family));
static char *print_flags
- PARAMS ((unsigned int, char *));
+ PARAMS ((struct cris_disasm_data *, unsigned int, char *));
static void print_with_operands
PARAMS ((const struct cris_opcode *, unsigned int, unsigned char *,
bfd_vma, disassemble_info *, const struct cris_opcode *,
unsigned int, unsigned char *, bfd_boolean));
static const struct cris_spec_reg *spec_reg_info
- PARAMS ((unsigned int));
+ PARAMS ((unsigned int, enum cris_disass_family));
static int print_insn_cris_generic
PARAMS ((bfd_vma, disassemble_info *, bfd_boolean));
static int print_insn_cris_with_register_prefix
PARAMS ((bfd_vma, disassemble_info *));
static int print_insn_cris_without_register_prefix
PARAMS ((bfd_vma, disassemble_info *));
+static int print_insn_crisv32_with_register_prefix
+ PARAMS ((bfd_vma, disassemble_info *));
+static int print_insn_crisv32_without_register_prefix
+ PARAMS ((bfd_vma, disassemble_info *));
+static int print_insn_crisv10_v32_with_register_prefix
+ PARAMS ((bfd_vma, disassemble_info *));
+static int print_insn_crisv10_v32_without_register_prefix
+ PARAMS ((bfd_vma, disassemble_info *));
+static bfd_boolean cris_parse_disassembler_options
+ PARAMS ((disassemble_info *, enum cris_disass_family));
static const struct cris_opcode *get_opcode_entry
- PARAMS ((unsigned int, unsigned int));
+ PARAMS ((unsigned int, unsigned int, struct cris_disasm_data *));
+
+/* Parse disassembler options and store state in info. FIXME: For the
+ time being, we abuse static variables. */
+
+static bfd_boolean
+cris_parse_disassembler_options (info, distype)
+ disassemble_info *info;
+ enum cris_disass_family distype;
+{
+ struct cris_disasm_data *disdata;
+
+ info->private_data = calloc (1, sizeof (struct cris_disasm_data));
+ disdata = (struct cris_disasm_data *) info->private_data;
+ if (disdata == NULL)
+ return FALSE;
+
+ /* Default true. */
+ disdata->trace_case
+ = (info->disassembler_options == NULL
+ || (strcmp (info->disassembler_options, "nocase") != 0));
+
+ disdata->distype = distype;
+ return TRUE;
+}
-/* Return the descriptor of a special register.
- FIXME: Depend on a CPU-version specific argument when all machinery
- is in place. */
static const struct cris_spec_reg *
-spec_reg_info (sreg)
+spec_reg_info (sreg, distype)
unsigned int sreg;
+ enum cris_disass_family distype;
{
int i;
for (i = 0; cris_spec_regs[i].name != NULL; i++)
{
if (cris_spec_regs[i].number == sreg)
- return &cris_spec_regs[i];
+ {
+ if (distype == cris_dis_v32)
+ switch (cris_spec_regs[i].applicable_version)
+ {
+ case cris_ver_warning:
+ case cris_ver_version_all:
+ case cris_ver_v3p:
+ case cris_ver_v8p:
+ case cris_ver_v10p:
+ case cris_ver_v32p:
+ /* No ambiguous sizes or register names with CRISv32. */
+ if (cris_spec_regs[i].warning == NULL)
+ return &cris_spec_regs[i];
+ default:
+ ;
+ }
+ else if (cris_spec_regs[i].applicable_version != cris_ver_v32p)
+ return &cris_spec_regs[i];
+ }
}
return NULL;
/* Get an entry in the opcode-table. */
static const struct cris_opcode *
-get_opcode_entry (insn, prefix_insn)
+get_opcode_entry (insn, prefix_insn, disdata)
unsigned int insn;
unsigned int prefix_insn;
+ struct cris_disasm_data *disdata;
{
/* For non-prefixed insns, we keep a table of pointers, indexed by the
insn code. Each entry is initialized when found to be NULL. */
/* Allocate and clear the opcode-table. */
if (opc_table == NULL)
{
- opc_table = xmalloc (65536 * sizeof (opc_table[0]));
+ opc_table = malloc (65536 * sizeof (opc_table[0]));
+ if (opc_table == NULL)
+ return NULL;
+
memset (opc_table, 0, 65536 * sizeof (const struct cris_opcode *));
dip_prefixes
- = xmalloc (65536 * sizeof (const struct cris_opcode **));
+ = malloc (65536 * sizeof (const struct cris_opcode **));
+ if (dip_prefixes == NULL)
+ return NULL;
+
memset (dip_prefixes, 0, 65536 * sizeof (dip_prefixes[0]));
bdapq_m1_prefixes
- = xmalloc (65536 * sizeof (const struct cris_opcode **));
+ = malloc (65536 * sizeof (const struct cris_opcode **));
+ if (bdapq_m1_prefixes == NULL)
+ return NULL;
+
memset (bdapq_m1_prefixes, 0, 65536 * sizeof (bdapq_m1_prefixes[0]));
bdapq_m2_prefixes
- = xmalloc (65536 * sizeof (const struct cris_opcode **));
+ = malloc (65536 * sizeof (const struct cris_opcode **));
+ if (bdapq_m2_prefixes == NULL)
+ return NULL;
+
memset (bdapq_m2_prefixes, 0, 65536 * sizeof (bdapq_m2_prefixes[0]));
bdapq_m4_prefixes
- = xmalloc (65536 * sizeof (const struct cris_opcode **));
+ = malloc (65536 * sizeof (const struct cris_opcode **));
+ if (bdapq_m4_prefixes == NULL)
+ return NULL;
+
memset (bdapq_m4_prefixes, 0, 65536 * sizeof (bdapq_m4_prefixes[0]));
rest_prefixes
- = xmalloc (65536 * sizeof (const struct cris_opcode **));
+ = malloc (65536 * sizeof (const struct cris_opcode **));
+ if (rest_prefixes == NULL)
+ return NULL;
+
memset (rest_prefixes, 0, 65536 * sizeof (rest_prefixes[0]));
}
const struct cris_opcode *popcodep
= (opc_table[prefix_insn] != NULL
? opc_table[prefix_insn]
- : get_opcode_entry (prefix_insn, NO_CRIS_PREFIX));
+ : get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata));
if (popcodep == NULL)
return NULL;
{
int level_of_match;
+ if (disdata->distype == cris_dis_v32)
+ {
+ switch (opcodep->applicable_version)
+ {
+ case cris_ver_version_all:
+ break;
+
+ case cris_ver_v0_3:
+ case cris_ver_v0_10:
+ case cris_ver_v3_10:
+ case cris_ver_sim_v0_10:
+ case cris_ver_v8_10:
+ case cris_ver_v10:
+ case cris_ver_warning:
+ continue;
+
+ case cris_ver_v3p:
+ case cris_ver_v8p:
+ case cris_ver_v10p:
+ case cris_ver_v32p:
+ break;
+
+ case cris_ver_v8:
+ abort ();
+ default:
+ abort ();
+ }
+ }
+ else
+ {
+ switch (opcodep->applicable_version)
+ {
+ case cris_ver_version_all:
+ case cris_ver_v0_3:
+ case cris_ver_v3p:
+ case cris_ver_v0_10:
+ case cris_ver_v8p:
+ case cris_ver_v8_10:
+ case cris_ver_v10:
+ case cris_ver_sim_v0_10:
+ case cris_ver_v10p:
+ case cris_ver_warning:
+ break;
+
+ case cris_ver_v32p:
+ continue;
+
+ case cris_ver_v8:
+ abort ();
+ default:
+ abort ();
+ }
+ }
+
/* We give a double lead for bits matching the template in
cris_opcodes. Not even, because then "move p8,r10" would
be given 2 bits lead over "clear.d r10". When there's a
&& ((level_of_match
= cris_constraint (opcodep->args,
insn,
- prefix_insn))
+ prefix_insn,
+ disdata))
>= 0)
&& ((level_of_match
+= 2 * number_of_bits (opcodep->match
/* Format number as hex with a leading "0x" into outbuffer. */
static char *
-format_hex (number, outbuffer)
+format_hex (number, outbuffer, disdata)
unsigned long number;
char *outbuffer;
+ struct cris_disasm_data *disdata;
{
/* Obfuscate to avoid warning on 32-bit host, but properly truncate
negative numbers on >32-bit hosts. */
/* Format the name of the general register regno into outbuffer. */
static char *
-format_reg (regno, outbuffer_start, with_reg_prefix)
+format_reg (disdata, regno, outbuffer_start, with_reg_prefix)
+ struct cris_disasm_data *disdata;
int regno;
char *outbuffer_start;
bfd_boolean with_reg_prefix;
switch (regno)
{
case 15:
- strcpy (outbuffer, "pc");
+ /* For v32, there is no context in which we output PC. */
+ if (disdata->distype == cris_dis_v32)
+ strcpy (outbuffer, "acr");
+ else
+ strcpy (outbuffer, "pc");
break;
case 14:
return outbuffer_start + strlen (outbuffer_start);
}
+/* Format the name of a support register into outbuffer. */
+
+static char *
+format_sup_reg (regno, outbuffer_start, with_reg_prefix)
+ unsigned int regno;
+ char *outbuffer_start;
+ bfd_boolean with_reg_prefix;
+{
+ char *outbuffer = outbuffer_start;
+ int i;
+
+ if (with_reg_prefix)
+ *outbuffer++ = REGISTER_PREFIX_CHAR;
+
+ for (i = 0; cris_support_regs[i].name != NULL; i++)
+ if (cris_support_regs[i].number == regno)
+ {
+ sprintf (outbuffer, "%s", cris_support_regs[i].name);
+ return outbuffer_start + strlen (outbuffer_start);
+ }
+
+ /* There's supposed to be register names covering all numbers, though
+ some may be generic names. */
+ sprintf (outbuffer, "format_sup_reg-BUG");
+ return outbuffer_start + strlen (outbuffer_start);
+}
+
/* Return -1 if the constraints of a bitwise-matched instruction say
that there is no match. Otherwise return a nonnegative number
indicating the confidence in the match (higher is better). */
static int
-cris_constraint (cs, insn, prefix_insn)
+cris_constraint (cs, insn, prefix_insn, disdata)
const char *cs;
unsigned int insn;
unsigned int prefix_insn;
+ struct cris_disasm_data *disdata;
{
int retval = 0;
int tmp;
switch (*s)
{
case '!':
- /* Do not recognize "pop" if there's a prefix. */
- if (prefix_insn != NO_CRIS_PREFIX)
+ /* Do not recognize "pop" if there's a prefix and then only for
+ v0..v10. */
+ if (prefix_insn != NO_CRIS_PREFIX
+ || disdata->distype != cris_dis_v0_v10)
return -1;
break;
+ case 'U':
+ /* Not recognized at disassembly. */
+ return -1;
+
case 'M':
/* Size modifier for "clear", i.e. special register 0, 4 or 8.
Check that it is one of them. Only special register 12 could
case 's':
case 'y':
+ case 'Y':
/* If this is a prefixed insn with postincrement (side-effect),
the prefix must not be DIP. */
if (prefix_insn != NO_CRIS_PREFIX)
if (insn & 0x400)
{
const struct cris_opcode *prefix_opcodep
- = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX);
+ = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata);
if (prefix_opcodep->match == DIP_OPCODE)
return -1;
{
/* Match the prefix insn to BDAPQ. */
const struct cris_opcode *prefix_opcodep
- = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX);
+ = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata);
if (prefix_opcodep->match == BDAP_QUICK_OPCODE)
{
{
unsigned int spec_reg = (insn >> 12) & 15;
const struct cris_spec_reg *sregp
- = spec_reg_info (spec_reg);
+ = spec_reg_info (spec_reg, disdata->distype);
/* For a special-register, the "prefix size" must
match the size of the register. */
case 'P':
{
const struct cris_spec_reg *sregp
- = spec_reg_info ((insn >> 12) & 15);
+ = spec_reg_info ((insn >> 12) & 15, disdata->distype);
/* Since we match four bits, we will give a value of 4-1 = 3
in a match. If there is a corresponding exact match of a
/* Return the length of an instruction. */
static unsigned
-bytes_to_skip (insn, matchedp)
+bytes_to_skip (insn, matchedp, distype)
unsigned int insn;
const struct cris_opcode *matchedp;
+ enum cris_disass_family distype;
{
/* Each insn is a word plus "immediate" operands. */
unsigned to_skip = 2;
const char *s;
for (s = template; *s; s++)
- if (*s == 's' && (insn & 0x400) && (insn & 15) == 15)
+ if ((*s == 's' || *s == 'N' || *s == 'Y')
+ && (insn & 0x400) && (insn & 15) == 15)
{
/* Immediate via [pc+], so we have to check the size of the
operand. */
else if (matchedp->imm_oprnd_size == SIZE_SPEC_REG)
{
const struct cris_spec_reg *sregp
- = spec_reg_info ((insn >> 12) & 15);
+ = spec_reg_info ((insn >> 12) & 15, distype);
/* FIXME: Improve error handling; should have been caught
earlier. */
if (sregp == NULL)
return 2;
- /* PC is incremented by two, not one, for a byte. */
- to_skip += (sregp->reg_size + 1) & ~1;
+ /* PC is incremented by two, not one, for a byte. Except on
+ CRISv32, where constants are always DWORD-size for
+ special registers. */
+ to_skip +=
+ distype == cris_dis_v32 ? 4 : (sregp->reg_size + 1) & ~1;
}
else
to_skip += (mode_size + 1) & ~1;
}
+ else if (*s == 'n')
+ to_skip += 4;
else if (*s == 'b')
to_skip += 2;
/* Print condition code flags. */
static char *
-print_flags (insn, cp)
+print_flags (disdata, insn, cp)
+ struct cris_disasm_data *disdata;
unsigned int insn;
char *cp;
{
/* Use the v8 (Etrax 100) flag definitions for disassembly.
The differences with v0 (Etrax 1..4) vs. Svinto are:
- v0 'd' <=> v8 'm'
- v0 'e' <=> v8 'b'. */
- static const char fnames[] = "cvznxibm";
+ v0 'd' <=> v8 'm'
+ v0 'e' <=> v8 'b'.
+ FIXME: Emit v0..v3 flag names somehow. */
+ static const char v8_fnames[] = "cvznxibm";
+ static const char v32_fnames[] = "cvznxiup";
+ const char *fnames
+ = disdata->distype == cris_dis_v32 ? v32_fnames : v8_fnames;
unsigned char flagbits = (((insn >> 8) & 0xf0) | (insn & 15));
int i;
static const char mode_char[] = "bwd?";
const char *s;
const char *cs;
+ struct cris_disasm_data *disdata
+ = (struct cris_disasm_data *) info->private_data;
/* Print out the name first thing we do. */
(*info->fprintf_func) (info->stream, "%s", opcodep->name);
{
switch (*s)
{
+ case 'T':
+ tp = format_sup_reg ((insn >> 12) & 15, tp, with_reg_prefix);
+ break;
+
+ case 'A':
+ if (with_reg_prefix)
+ *tp++ = REGISTER_PREFIX_CHAR;
+ *tp++ = 'a';
+ *tp++ = 'c';
+ *tp++ = 'r';
+ break;
+
+ case '[':
+ case ']':
case ',':
*tp++ = *s;
break;
case '!':
- /* Ignore at this point; used at earlier stages to avoid recognition
- if there's a prefixes at something that in other ways looks like
- a "pop". */
+ /* Ignore at this point; used at earlier stages to avoid
+ recognition if there's a prefix at something that in other
+ ways looks like a "pop". */
+ break;
+
+ case 'd':
+ /* Ignore. This is an optional ".d " on the large one of
+ relaxable insns. */
break;
case 'B':
case 'D':
case 'r':
- tp = format_reg (insn & 15, tp, with_reg_prefix);
+ tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
break;
case 'R':
- tp = format_reg ((insn >> 12) & 15, tp, with_reg_prefix);
+ tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
+ break;
+
+ case 'n':
+ {
+ /* Like N but pc-relative to the start of the insn. */
+ unsigned long number
+ = (buffer[2] + buffer[3] * 256 + buffer[4] * 65536
+ + buffer[5] * 0x1000000 + addr);
+
+ /* Finish off and output previous formatted bytes. */
+ *tp = 0;
+ if (temp[0])
+ (*info->fprintf_func) (info->stream, "%s", temp);
+ tp = temp;
+
+ (*info->print_address_func) ((bfd_vma) number, info);
+ }
+ break;
+
+ case 'u':
+ {
+ /* Like n but the offset is bits <3:0> in the instruction. */
+ unsigned long number = (buffer[0] & 0xf) * 2 + addr;
+
+ /* Finish off and output previous formatted bytes. */
+ *tp = 0;
+ if (temp[0])
+ (*info->fprintf_func) (info->stream, "%s", temp);
+ tp = temp;
+
+ (*info->print_address_func) ((bfd_vma) number, info);
+ }
break;
+ case 'N':
case 'y':
+ case 'Y':
case 'S':
case 's':
/* Any "normal" memory operand. */
else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG)
{
const struct cris_spec_reg *sregp
- = spec_reg_info ((insn >> 12) & 15);
+ = spec_reg_info ((insn >> 12) & 15, disdata->distype);
/* A NULL return should have been as a non-match earlier,
so catch it as an internal error in the error-case
/* Whatever non-valid size. */
nbytes = 42;
else
- /* PC is always incremented by a multiple of two. */
- nbytes = (sregp->reg_size + 1) & ~1;
+ /* PC is always incremented by a multiple of two.
+ For CRISv32, immediates are always 4 bytes for
+ special registers. */
+ nbytes = disdata->distype == cris_dis_v32
+ ? 4 : (sregp->reg_size + 1) & ~1;
}
else
{
info->target = number;
}
else
- tp = format_hex (number, tp);
+ tp = format_hex (number, tp, disdata);
}
}
else
else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG)
{
const struct cris_spec_reg *sregp
- = spec_reg_info ((insn >> 12) & 15);
+ = spec_reg_info ((insn >> 12) & 15, disdata->distype);
/* FIXME: Improve error handling; should have been caught
earlier. */
{
if (insn & 0x400)
{
- tp = format_reg (insn & 15, tp, with_reg_prefix);
+ tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
*tp++ = '=';
}
info->target2 = prefix_insn & 15;
*tp++ = '[';
- tp = format_reg (prefix_insn & 15, tp,
+ tp = format_reg (disdata, prefix_insn & 15, tp,
with_reg_prefix);
if (prefix_insn & 0x400)
*tp++ = '+';
number -= 256;
/* Output "reg+num" or, if num < 0, "reg-num". */
- tp = format_reg ((prefix_insn >> 12) & 15, tp,
+ tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
with_reg_prefix);
if (number >= 0)
*tp++ = '+';
case BIAP_OPCODE:
/* Output "r+R.m". */
- tp = format_reg (prefix_insn & 15, tp, with_reg_prefix);
+ tp = format_reg (disdata, prefix_insn & 15, tp,
+ with_reg_prefix);
*tp++ = '+';
- tp = format_reg ((prefix_insn >> 12) & 15, tp,
+ tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
with_reg_prefix);
*tp++ = '.';
*tp++ = mode_char[(prefix_insn >> 4) & 3];
case BDAP_INDIR_OPCODE:
/* Output "r+s.m", or, if "s" is [pc+], "r+s" or
"r-s". */
- tp = format_reg ((prefix_insn >> 12) & 15, tp,
+ tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
with_reg_prefix);
if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15)
/* Output "r+[R].m" or "r+[R+].m". */
*tp++ = '+';
*tp++ = '[';
- tp = format_reg (prefix_insn & 15, tp,
+ tp = format_reg (disdata, prefix_insn & 15, tp,
with_reg_prefix);
if (prefix_insn & 0x400)
*tp++ = '+';
}
else
{
- tp = format_reg (insn & 15, tp, with_reg_prefix);
+ tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
info->target = insn & 15;
break;
case 'x':
- tp = format_reg ((insn >> 12) & 15, tp, with_reg_prefix);
+ tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
*tp++ = '.';
*tp++ = mode_char[(insn >> 4) & 3];
break;
if (where > 32767)
where -= 65536;
- where += addr + 4;
+ where += addr + ((disdata->distype == cris_dis_v32) ? 0 : 4);
if (insn == BA_PC_INCR_OPCODE)
info->insn_type = dis_branch;
case 'o':
{
long offset = insn & 0xfe;
+ bfd_vma target;
if (insn & 1)
offset |= ~0xff;
else
info->insn_type = dis_condbranch;
- info->target = (bfd_vma) (addr + 2 + offset);
+ target = addr + ((disdata->distype == cris_dis_v32) ? 0 : 2) + offset;
+ info->target = target;
*tp = 0;
tp = temp;
(*info->fprintf_func) (info->stream, "%s", temp);
-
- (*info->print_address_func) ((bfd_vma) (addr + 2 + offset), info);
+ (*info->print_address_func) (target, info);
}
break;
+ case 'Q':
case 'O':
{
long number = buffer[0];
tp = format_dec (number, tp, 1);
*tp++ = ',';
- tp = format_reg ((insn >> 12) & 15, tp, with_reg_prefix);
+ tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
}
break;
case 'f':
- tp = print_flags (insn, tp);
+ tp = print_flags (disdata, insn, tp);
break;
case 'i':
case 'P':
{
const struct cris_spec_reg *sregp
- = spec_reg_info ((insn >> 12) & 15);
+ = spec_reg_info ((insn >> 12) & 15, disdata->distype);
if (sregp->name == NULL)
/* Should have been caught as a non-match eariler. */
unsigned int insn;
const struct cris_opcode *matchedp;
int advance = 0;
+ struct cris_disasm_data *disdata
+ = (struct cris_disasm_data *) info->private_data;
/* No instruction will be disassembled as longer than this number of
bytes; stacked prefixes will not be expanded. */
valid "bcc .+2" insn, it is also useless enough and enough
of a nuiscance that we will just output "bcc .+2" for it
and signal it as a noninsn. */
- (*info->fprintf_func) (info->stream, "bcc .+2");
+ (*info->fprintf_func) (info->stream,
+ disdata->distype == cris_dis_v32
+ ? "bcc ." : "bcc .+2");
info->insn_type = dis_noninsn;
advance += 2;
}
unsigned int prefix_insn = insn;
int prefix_size = 0;
- matchedp = get_opcode_entry (insn, NO_CRIS_PREFIX);
+ matchedp = get_opcode_entry (insn, NO_CRIS_PREFIX, disdata);
/* Check if we're supposed to write out prefixes as address
modes and if this was a prefix. */
{
/* If it's a prefix, put it into the prefix vars and get the
main insn. */
- prefix_size = bytes_to_skip (prefix_insn, matchedp);
+ prefix_size = bytes_to_skip (prefix_insn, matchedp,
+ disdata->distype);
prefix_opcodep = matchedp;
insn = bufp[prefix_size] + bufp[prefix_size + 1] * 256;
- matchedp = get_opcode_entry (insn, prefix_insn);
+ matchedp = get_opcode_entry (insn, prefix_insn, disdata);
if (matchedp != NULL)
{
}
else
{
- advance += bytes_to_skip (insn, matchedp);
+ advance += bytes_to_skip (insn, matchedp, disdata->distype);
/* The info_type and assorted fields will be set according
to the operands. */
return advance;
}
-/* Disassemble, prefixing register names with `$'. */
+/* Disassemble, prefixing register names with `$'. CRIS v0..v10. */
static int
print_insn_cris_with_register_prefix (vma, info)
bfd_vma vma;
disassemble_info *info;
{
+ if (info->private_data == NULL
+ && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
+ return -1;
+ return print_insn_cris_generic (vma, info, TRUE);
+}
+
+/* Disassemble, prefixing register names with `$'. CRIS v32. */
+
+static int
+print_insn_crisv32_with_register_prefix (vma, info)
+ bfd_vma vma;
+ disassemble_info *info;
+{
+ if (info->private_data == NULL
+ && !cris_parse_disassembler_options (info, cris_dis_v32))
+ return -1;
+ return print_insn_cris_generic (vma, info, TRUE);
+}
+
+/* Disassemble, prefixing register names with `$'.
+ Common v10 and v32 subset. */
+
+static int
+print_insn_crisv10_v32_with_register_prefix (vma, info)
+ bfd_vma vma;
+ disassemble_info *info;
+{
+ if (info->private_data == NULL
+ && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
+ return -1;
return print_insn_cris_generic (vma, info, TRUE);
}
-/* Disassemble, no prefixes on register names. */
+/* Disassemble, no prefixes on register names. CRIS v0..v10. */
static int
print_insn_cris_without_register_prefix (vma, info)
bfd_vma vma;
disassemble_info *info;
{
+ if (info->private_data == NULL
+ && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
+ return -1;
+ return print_insn_cris_generic (vma, info, FALSE);
+}
+
+/* Disassemble, no prefixes on register names. CRIS v32. */
+
+static int
+print_insn_crisv32_without_register_prefix (vma, info)
+ bfd_vma vma;
+ disassemble_info *info;
+{
+ if (info->private_data == NULL
+ && !cris_parse_disassembler_options (info, cris_dis_v32))
+ return -1;
+ return print_insn_cris_generic (vma, info, FALSE);
+}
+
+/* Disassemble, no prefixes on register names.
+ Common v10 and v32 subset. */
+
+static int
+print_insn_crisv10_v32_without_register_prefix (vma, info)
+ bfd_vma vma;
+ disassemble_info *info;
+{
+ if (info->private_data == NULL
+ && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
+ return -1;
return print_insn_cris_generic (vma, info, FALSE);
}
/* Return a disassembler-function that prints registers with a `$' prefix,
- or one that prints registers without a prefix. */
+ or one that prints registers without a prefix.
+ FIXME: We should improve the solution to avoid the multitude of
+ functions seen above. */
disassembler_ftype
cris_get_disassembler (abfd)
{
/* If there's no bfd in sight, we return what is valid as input in all
contexts if fed back to the assembler: disassembly *with* register
- prefix. */
- if (abfd == NULL || bfd_get_symbol_leading_char (abfd) == 0)
+ prefix. Unfortunately this will be totally wrong for v32. */
+ if (abfd == NULL)
return print_insn_cris_with_register_prefix;
+ if (bfd_get_symbol_leading_char (abfd) == 0)
+ {
+ if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
+ return print_insn_crisv32_with_register_prefix;
+ if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
+ return print_insn_crisv10_v32_with_register_prefix;
+
+ /* We default to v10. This may be specifically specified in the
+ bfd mach, but is also the default setting. */
+ return print_insn_cris_with_register_prefix;
+ }
+
+ if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
+ return print_insn_crisv32_without_register_prefix;
+ if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
+ return print_insn_crisv10_v32_without_register_prefix;
return print_insn_cris_without_register_prefix;
}
#define NULL (0)
#endif
+/* This table isn't used for CRISv32 and the size of immediate operands. */
const struct cris_spec_reg
cris_spec_regs[] =
{
+ {"bz", 0, 1, cris_ver_v32p, NULL},
{"p0", 0, 1, 0, NULL},
{"vr", 1, 1, 0, NULL},
{"p1", 1, 1, 0, NULL},
+ {"pid", 2, 1, cris_ver_v32p, NULL},
+ {"p2", 2, 1, cris_ver_v32p, NULL},
{"p2", 2, 1, cris_ver_warning, NULL},
+ {"srs", 3, 1, cris_ver_v32p, NULL},
+ {"p3", 3, 1, cris_ver_v32p, NULL},
{"p3", 3, 1, cris_ver_warning, NULL},
+ {"wz", 4, 2, cris_ver_v32p, NULL},
{"p4", 4, 2, 0, NULL},
- {"ccr", 5, 2, 0, NULL},
- {"p5", 5, 2, 0, NULL},
+ {"ccr", 5, 2, cris_ver_v0_10, NULL},
+ {"exs", 5, 4, cris_ver_v32p, NULL},
+ {"p5", 5, 2, cris_ver_v0_10, NULL},
+ {"p5", 5, 4, cris_ver_v32p, NULL},
{"dcr0",6, 2, cris_ver_v0_3, NULL},
+ {"eda", 6, 4, cris_ver_v32p, NULL},
{"p6", 6, 2, cris_ver_v0_3, NULL},
+ {"p6", 6, 4, cris_ver_v32p, NULL},
{"dcr1/mof", 7, 4, cris_ver_v10p,
"Register `dcr1/mof' with ambiguous size specified. Guessing 4 bytes"},
{"dcr1/mof", 7, 2, cris_ver_v0_3,
{"dcr1",7, 2, cris_ver_v0_3, NULL},
{"p7", 7, 4, cris_ver_v10p, NULL},
{"p7", 7, 2, cris_ver_v0_3, NULL},
+ {"dz", 8, 4, cris_ver_v32p, NULL},
{"p8", 8, 4, 0, NULL},
- {"ibr", 9, 4, 0, NULL},
+ {"ibr", 9, 4, cris_ver_v0_10, NULL},
+ {"ebp", 9, 4, cris_ver_v32p, NULL},
{"p9", 9, 4, 0, NULL},
- {"irp", 10, 4, 0, NULL},
+ {"irp", 10, 4, cris_ver_v0_10, NULL},
+ {"erp", 10, 4, cris_ver_v32p, NULL},
{"p10", 10, 4, 0, NULL},
{"srp", 11, 4, 0, NULL},
{"p11", 11, 4, 0, NULL},
/* For disassembly use only. Accept at assembly with a warning. */
{"bar/dtp0", 12, 4, cris_ver_warning,
"Ambiguous register `bar/dtp0' specified"},
- {"bar", 12, 4, cris_ver_v8p, NULL},
+ {"nrp", 12, 4, cris_ver_v32p, NULL},
+ {"bar", 12, 4, cris_ver_v8_10, NULL},
{"dtp0",12, 4, cris_ver_v0_3, NULL},
{"p12", 12, 4, 0, NULL},
/* For disassembly use only. Accept at assembly with a warning. */
{"dccr/dtp1",13, 4, cris_ver_warning,
"Ambiguous register `dccr/dtp1' specified"},
- {"dccr",13, 4, cris_ver_v8p, NULL},
+ {"ccs", 13, 4, cris_ver_v32p, NULL},
+ {"dccr",13, 4, cris_ver_v8_10, NULL},
{"dtp1",13, 4, cris_ver_v0_3, NULL},
{"p13", 13, 4, 0, NULL},
- {"brp", 14, 4, cris_ver_v3p, NULL},
+ {"brp", 14, 4, cris_ver_v3_10, NULL},
+ {"usp", 14, 4, cris_ver_v32p, NULL},
{"p14", 14, 4, cris_ver_v3p, NULL},
- {"usp", 15, 4, cris_ver_v10p, NULL},
+ {"usp", 15, 4, cris_ver_v10, NULL},
+ {"spc", 15, 4, cris_ver_v32p, NULL},
{"p15", 15, 4, cris_ver_v10p, NULL},
{NULL, 0, 0, cris_ver_version_all, NULL}
};
+/* Add version specifiers to this table when necessary.
+ The (now) regular coding of register names suggests a simpler
+ implementation. */
+const struct cris_support_reg cris_support_regs[] =
+{
+ {"s0", 0},
+ {"s1", 1},
+ {"s2", 2},
+ {"s3", 3},
+ {"s4", 4},
+ {"s5", 5},
+ {"s6", 6},
+ {"s7", 7},
+ {"s8", 8},
+ {"s9", 9},
+ {"s10", 10},
+ {"s11", 11},
+ {"s12", 12},
+ {"s13", 13},
+ {"s14", 14},
+ {"s15", 15},
+ {NULL, 0}
+};
+
/* All CRIS opcodes are 16 bits.
- The match component is a mask saying which bits must match a
and disassembly.
Operand-matching characters:
+ [ ] , space
+ Verbatim.
+ A The string "ACR" (case-insensitive).
B Not really an operand. It causes a "BDAP -size,SP" prefix to be
- output for the PUSH alias-instructions and recognizes a
- push-prefix at disassembly. Must be followed by a R or P letter.
+ output for the PUSH alias-instructions and recognizes a push-
+ prefix at disassembly. This letter isn't recognized for v32.
+ Must be followed by a R or P letter.
! Non-match pattern, will not match if there's a prefix insn.
b Non-matching operand, used for branches with 16-bit
displacement. Only recognized by the disassembler.
c 5-bit unsigned immediate in bits <4:0>.
C 4-bit unsigned immediate in bits <3:0>.
+ d At assembly, optionally (as in put other cases before this one)
+ ".d" or ".D" at the start of the operands, followed by one space
+ character. At disassembly, nothing.
D General register in bits <15:12> and <3:0>.
f List of flags in bits <15:12> and <3:0>.
i 6-bit signed immediate in bits <5:0>.
I 6-bit unsigned immediate in bits <5:0>.
M Size modifier (B, W or D) for CLEAR instructions.
m Size modifier (B, W or D) in bits <5:4>
+ N A 32-bit dword, like in the difference between s and y.
+ This has no effect on bits in the opcode. Can also be expressed
+ as "[pc+]" in input.
+ n As N, but PC-relative (to the start of the instruction).
o [-128..127] word offset in bits <7:1> and <0>. Used by 8-bit
branch instructions.
O [-128..127] offset in bits <7:0>. Also matches a comma and a
- general register after the expression. Used only for the BDAP
- prefix insn.
+ general register after the expression, in bits <15:12>. Used
+ only for the BDAP prefix insn (in v32 the ADDOQ insn; same opcode).
P Special register in bits <15:12>.
p Indicates that the insn is a prefix insn. Must be first
character.
+ Q As O, but don't relax; force an 8-bit offset.
R General register in bits <15:12>.
r General register in bits <3:0>.
S Source operand in bit <10> and a prefix; a 3-operand prefix
without side-effect.
s Source operand in bits <10> and <3:0>, optionally with a
- side-effect prefix.
+ side-effect prefix, except [pc] (the name, not R15 as in ACR)
+ isn't allowed for v32 and higher.
+ T Support register in bits <15:12>.
+ u 4-bit (PC-relative) unsigned immediate word offset in bits <3:0>.
+ U Relaxes to either u or n, instruction is assumed LAPCQ or LAPC.
+ Not recognized at disassembly.
x Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>.
y Like 's' but do not allow an integer at assembly.
+ Y The difference s-y; only an integer is allowed.
z Size modifier (B or W) in bit <4>. */
/* Please note the order of the opcodes in this table is significant.
The assembler requires that all instances of the same mnemonic must
be consecutive. If they aren't, the assembler might not recognize
- them, or may indicate and internal error.
+ them, or may indicate an internal error.
The disassembler should not normally care about the order of the
opcodes, but will prefer an earlier alternative if the "match-score"
{"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, 0,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"add", 0x0A00, 0x01c0, "m S,D", 0, SIZE_NONE, 0,
+ {"add", 0x0A00, 0x01c0, "m S,D", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"add", 0x0a00, 0x05c0, "m S,R,r", 0, SIZE_NONE, 0,
+ {"add", 0x0a00, 0x05c0, "m S,R,r", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_three_operand_add_sub_cmp_and_or_op},
+ {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD,
+ cris_ver_v32p,
+ cris_none_reg_mode_add_sub_cmp_and_or_move_op},
+
+ {"addc", 0x0570, 0x0A80, "r,R", 0, SIZE_FIX_32,
+ cris_ver_v32p,
+ cris_not_implemented_op},
+
+ {"addc", 0x09A0, 0x0250, "s,R", 0, SIZE_FIX_32,
+ cris_ver_v32p,
+ cris_not_implemented_op},
+
+ {"addi", 0x0540, 0x0A80, "x,r,A", 0, SIZE_NONE,
+ cris_ver_v32p,
+ cris_addi_op},
+
{"addi", 0x0500, 0x0Ac0, "x,r", 0, SIZE_NONE, 0,
cris_addi_op},
+ /* This collates after "addo", but we want to disassemble as "addoq",
+ not "addo". */
+ {"addoq", 0x0100, 0x0E00, "Q,A", 0, SIZE_NONE,
+ cris_ver_v32p,
+ cris_not_implemented_op},
+
+ {"addo", 0x0940, 0x0280, "m s,R,A", 0, SIZE_FIELD_SIGNED,
+ cris_ver_v32p,
+ cris_not_implemented_op},
+
+ /* This must be located after the insn above, lest we misinterpret
+ "addo.b -1,r0,acr" as "addo .b-1,r0,acr". FIXME: Sounds like a
+ parser bug. */
+ {"addo", 0x0100, 0x0E00, "O,A", 0, SIZE_NONE,
+ cris_ver_v32p,
+ cris_not_implemented_op},
+
{"addq", 0x0200, 0x0Dc0, "I,R", 0, SIZE_NONE, 0,
cris_quick_mode_add_sub_op},
{"adds", 0x0420, 0x0Bc0, "z r,R", 0, SIZE_NONE, 0,
cris_reg_mode_add_sub_cmp_and_or_move_op},
+ /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
{"adds", 0x0820, 0x03c0, "z s,R", 0, SIZE_FIELD, 0,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"adds", 0x0820, 0x03c0, "z S,D", 0, SIZE_NONE, 0,
+ {"adds", 0x0820, 0x03c0, "z S,D", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"adds", 0x0820, 0x07c0, "z S,R,r", 0, SIZE_NONE, 0,
+ {"adds", 0x0820, 0x07c0, "z S,R,r", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_three_operand_add_sub_cmp_and_or_op},
{"addu", 0x0400, 0x0be0, "z r,R", 0, SIZE_NONE, 0,
cris_reg_mode_add_sub_cmp_and_or_move_op},
+ /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
{"addu", 0x0800, 0x03e0, "z s,R", 0, SIZE_FIELD, 0,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"addu", 0x0800, 0x03e0, "z S,D", 0, SIZE_NONE, 0,
+ {"addu", 0x0800, 0x03e0, "z S,D", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"addu", 0x0800, 0x07e0, "z S,R,r", 0, SIZE_NONE, 0,
+ {"addu", 0x0800, 0x07e0, "z S,R,r", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_three_operand_add_sub_cmp_and_or_op},
{"and", 0x0700, 0x08C0, "m r,R", 0, SIZE_NONE, 0,
{"and", 0x0B00, 0x00C0, "m s,R", 0, SIZE_FIELD, 0,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"and", 0x0B00, 0x00C0, "m S,D", 0, SIZE_NONE, 0,
+ {"and", 0x0B00, 0x00C0, "m S,D", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"and", 0x0B00, 0x04C0, "m S,R,r", 0, SIZE_NONE, 0,
+ {"and", 0x0B00, 0x04C0, "m S,R,r", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_three_operand_add_sub_cmp_and_or_op},
{"andq", 0x0300, 0x0CC0, "i,R", 0, SIZE_NONE, 0,
0x0F00+(0xF-CC_A)*0x1000, "o", 1, SIZE_NONE, 0,
cris_eight_bit_offset_branch_op},
+ /* Needs to come after the usual "ba o", which might be relaxed to
+ this one. */
+ {"ba", BA_DWORD_OPCODE,
+ 0xffff & (~BA_DWORD_OPCODE), "n", 0, SIZE_FIX_32,
+ cris_ver_v32p,
+ cris_none_reg_mode_jump_op},
+
+ {"bas", 0x0EBF, 0x0140, "n,P", 0, SIZE_FIX_32,
+ cris_ver_v32p,
+ cris_none_reg_mode_jump_op},
+
+ {"basc", 0x0EFF, 0x0100, "n,P", 0, SIZE_FIX_32,
+ cris_ver_v32p,
+ cris_none_reg_mode_jump_op},
+
{"bcc",
BRANCH_QUICK_OPCODE+CC_CC*0x1000,
0x0f00+(0xF-CC_CC)*0x1000, "o", 1, SIZE_NONE, 0,
cris_eight_bit_offset_branch_op},
{"bdap",
- BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS, "pm s,R", 0, SIZE_FIELD, 0,
+ BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS, "pm s,R", 0, SIZE_FIELD_SIGNED,
+ cris_ver_v0_10,
cris_bdap_prefix},
{"bdap",
- BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS, "pO", 0, SIZE_NONE, 0,
+ BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS, "pO", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_quick_mode_bdap_prefix},
{"beq",
cris_eight_bit_offset_branch_op},
/* This is deliberately put before "bext" to trump it, even though not
- in alphabetical order. */
+ in alphabetical order, since we don't do excluding version checks
+ for v0..v10. */
{"bwf",
BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
- cris_ver_v10p,
+ cris_ver_v10,
cris_eight_bit_offset_branch_op},
{"bext",
0x0f00+(0xF-CC_HS)*0x1000, "o", 1, SIZE_NONE, 0,
cris_eight_bit_offset_branch_op},
- {"biap", BIAP_OPCODE, BIAP_Z_BITS, "pm r,R", 0, SIZE_NONE, 0,
+ {"biap", BIAP_OPCODE, BIAP_Z_BITS, "pm r,R", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_biap_prefix},
{"ble",
cris_eight_bit_offset_branch_op},
{"bmod", 0x0ab0, 0x0140, "s,R", 0, SIZE_FIX_32,
- cris_ver_sim,
+ cris_ver_sim_v0_10,
cris_not_implemented_op},
{"bmod", 0x0ab0, 0x0140, "S,D", 0, SIZE_NONE,
- cris_ver_sim,
+ cris_ver_sim_v0_10,
cris_not_implemented_op},
{"bmod", 0x0ab0, 0x0540, "S,R,r", 0, SIZE_NONE,
- cris_ver_sim,
+ cris_ver_sim_v0_10,
cris_not_implemented_op},
{"bne",
{"bound", 0x05c0, 0x0A00, "m r,R", 0, SIZE_NONE, 0,
cris_two_operand_bound_op},
- {"bound", 0x09c0, 0x0200, "m s,R", 0, SIZE_FIELD, 0,
+ /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
+ {"bound", 0x09c0, 0x0200, "m s,R", 0, SIZE_FIELD,
+ cris_ver_v0_10,
cris_two_operand_bound_op},
- {"bound", 0x09c0, 0x0200, "m S,D", 0, SIZE_NONE, 0,
+ /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
+ {"bound", 0x0dcf, 0x0200, "m Y,R", 0, SIZE_FIELD, 0,
cris_two_operand_bound_op},
- {"bound", 0x09c0, 0x0600, "m S,R,r", 0, SIZE_NONE, 0,
+ {"bound", 0x09c0, 0x0200, "m S,D", 0, SIZE_NONE,
+ cris_ver_v0_10,
+ cris_two_operand_bound_op},
+ {"bound", 0x09c0, 0x0600, "m S,R,r", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_three_operand_bound_op},
+
{"bpl",
BRANCH_QUICK_OPCODE+CC_PL*0x1000,
0x0f00+(0xF-CC_PL)*0x1000, "o", 1, SIZE_NONE, 0,
cris_ver_v3p,
cris_break_op},
+ {"bsb",
+ BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
+ 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
+ cris_ver_v32p,
+ cris_eight_bit_offset_branch_op},
+
+ {"bsr", 0xBEBF, 0x4140, "n", 0, SIZE_FIX_32,
+ cris_ver_v32p,
+ cris_none_reg_mode_jump_op},
+
+ {"bsrc", 0xBEFF, 0x4100, "n", 0, SIZE_FIX_32,
+ cris_ver_v32p,
+ cris_none_reg_mode_jump_op},
+
{"bstore", 0x0af0, 0x0100, "s,R", 0, SIZE_FIX_32,
cris_ver_warning,
cris_not_implemented_op},
cris_btst_nop_op},
{"btstq", 0x0380, 0x0C60, "c,R", 0, SIZE_NONE, 0,
cris_btst_nop_op},
+
{"bvc",
BRANCH_QUICK_OPCODE+CC_VC*0x1000,
0x0f00+(0xF-CC_VC)*0x1000, "o", 1, SIZE_NONE, 0,
{"clear", 0x0A70, 0x3180, "M y", 0, SIZE_NONE, 0,
cris_none_reg_mode_clear_test_op},
- {"clear", 0x0A70, 0x3180, "M S", 0, SIZE_NONE, 0,
+ {"clear", 0x0A70, 0x3180, "M S", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_none_reg_mode_clear_test_op},
{"clearf", 0x05F0, 0x0A00, "f", 0, SIZE_NONE, 0,
{"cmp", 0x0Ac0, 0x0100, "m s,R", 0, SIZE_FIELD, 0,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"cmp", 0x0Ac0, 0x0100, "m S,D", 0, SIZE_NONE, 0,
+ {"cmp", 0x0Ac0, 0x0100, "m S,D", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
{"cmpq", 0x02C0, 0x0D00, "i,R", 0, SIZE_NONE, 0,
cris_quick_mode_and_cmp_move_or_op},
+ /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
{"cmps", 0x08e0, 0x0300, "z s,R", 0, SIZE_FIELD, 0,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"cmps", 0x08e0, 0x0300, "z S,D", 0, SIZE_NONE, 0,
+ {"cmps", 0x08e0, 0x0300, "z S,D", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
+ /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
{"cmpu", 0x08c0, 0x0320, "z s,R" , 0, SIZE_FIELD, 0,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"cmpu", 0x08c0, 0x0320, "z S,D", 0, SIZE_NONE, 0,
+ {"cmpu", 0x08c0, 0x0320, "z S,D", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
{"di", 0x25F0, 0xDA0F, "", 0, SIZE_NONE, 0,
cris_clearf_di_op},
- {"dip", DIP_OPCODE, DIP_Z_BITS, "ps", 0, SIZE_FIX_32, 0,
+ {"dip", DIP_OPCODE, DIP_Z_BITS, "ps", 0, SIZE_FIX_32,
+ cris_ver_v0_10,
cris_dip_prefix},
{"div", 0x0980, 0x0640, "m R,r", 0, SIZE_FIELD, 0,
{"ei", 0x25B0, 0xDA4F, "", 0, SIZE_NONE, 0,
cris_ax_ei_setf_op},
+ {"fidxd", 0x0ab0, 0xf540, "[r]", 0, SIZE_NONE,
+ cris_ver_v32p,
+ cris_not_implemented_op},
+
+ {"fidxi", 0x0d30, 0xF2C0, "[r]", 0, SIZE_NONE,
+ cris_ver_v32p,
+ cris_not_implemented_op},
+
+ {"ftagd", 0x1AB0, 0xE540, "[r]", 0, SIZE_NONE,
+ cris_ver_v32p,
+ cris_not_implemented_op},
+
+ {"ftagi", 0x1D30, 0xE2C0, "[r]", 0, SIZE_NONE,
+ cris_ver_v32p,
+ cris_not_implemented_op},
+
+ {"halt", 0xF930, 0x06CF, "", 0, SIZE_NONE,
+ cris_ver_v32p,
+ cris_not_implemented_op},
+
+ {"jas", 0x09B0, 0x0640, "r,P", 0, SIZE_NONE,
+ cris_ver_v32p,
+ cris_reg_mode_jump_op},
+
+ {"jas", 0x0DBF, 0x0240, "N,P", 0, SIZE_FIX_32,
+ cris_ver_v32p,
+ cris_reg_mode_jump_op},
+
+ {"jasc", 0x0B30, 0x04C0, "r,P", 0, SIZE_NONE,
+ cris_ver_v32p,
+ cris_reg_mode_jump_op},
+
+ {"jasc", 0x0F3F, 0x00C0, "N,P", 0, SIZE_FIX_32,
+ cris_ver_v32p,
+ cris_reg_mode_jump_op},
+
{"jbrc", 0x69b0, 0x9640, "r", 0, SIZE_NONE,
- cris_ver_v8p,
+ cris_ver_v8_10,
cris_reg_mode_jump_op},
{"jbrc", 0x6930, 0x92c0, "s", 0, SIZE_FIX_32,
- cris_ver_v8p,
+ cris_ver_v8_10,
cris_none_reg_mode_jump_op},
{"jbrc", 0x6930, 0x92c0, "S", 0, SIZE_NONE,
- cris_ver_v8p,
+ cris_ver_v8_10,
cris_none_reg_mode_jump_op},
- {"jir", 0xA9b0, 0x5640, "r", 0, SIZE_NONE, 0,
+ {"jir", 0xA9b0, 0x5640, "r", 0, SIZE_NONE,
+ cris_ver_v8_10,
cris_reg_mode_jump_op},
- {"jir", 0xA930, 0x52c0, "s", 0, SIZE_FIX_32, 0,
+ {"jir", 0xA930, 0x52c0, "s", 0, SIZE_FIX_32,
+ cris_ver_v8_10,
cris_none_reg_mode_jump_op},
- {"jir", 0xA930, 0x52c0, "S", 0, SIZE_NONE, 0,
+ {"jir", 0xA930, 0x52c0, "S", 0, SIZE_NONE,
+ cris_ver_v8_10,
cris_none_reg_mode_jump_op},
{"jirc", 0x29b0, 0xd640, "r", 0, SIZE_NONE,
- cris_ver_v8p,
+ cris_ver_v8_10,
cris_reg_mode_jump_op},
{"jirc", 0x2930, 0xd2c0, "s", 0, SIZE_FIX_32,
- cris_ver_v8p,
+ cris_ver_v8_10,
cris_none_reg_mode_jump_op},
{"jirc", 0x2930, 0xd2c0, "S", 0, SIZE_NONE,
- cris_ver_v8p,
+ cris_ver_v8_10,
cris_none_reg_mode_jump_op},
{"jsr", 0xB9b0, 0x4640, "r", 0, SIZE_NONE, 0,
cris_reg_mode_jump_op},
- {"jsr", 0xB930, 0x42c0, "s", 0, SIZE_FIX_32, 0,
+ {"jsr", 0xB930, 0x42c0, "s", 0, SIZE_FIX_32,
+ cris_ver_v0_10,
cris_none_reg_mode_jump_op},
- {"jsr", 0xB930, 0x42c0, "S", 0, SIZE_NONE, 0,
+ {"jsr", 0xBDBF, 0x4240, "N", 0, SIZE_FIX_32,
+ cris_ver_v32p,
+ cris_none_reg_mode_jump_op},
+
+ {"jsr", 0xB930, 0x42c0, "S", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_none_reg_mode_jump_op},
{"jsrc", 0x39b0, 0xc640, "r", 0, SIZE_NONE,
- cris_ver_v8p,
+ cris_ver_v8_10,
cris_reg_mode_jump_op},
{"jsrc", 0x3930, 0xc2c0, "s", 0, SIZE_FIX_32,
- cris_ver_v8p,
+ cris_ver_v8_10,
cris_none_reg_mode_jump_op},
{"jsrc", 0x3930, 0xc2c0, "S", 0, SIZE_NONE,
- cris_ver_v8p,
+ cris_ver_v8_10,
cris_none_reg_mode_jump_op},
+ {"jsrc", 0xBB30, 0x44C0, "r", 0, SIZE_NONE,
+ cris_ver_v32p,
+ cris_reg_mode_jump_op},
+
+ {"jsrc", 0xBF3F, 0x40C0, "N", 0, SIZE_FIX_32,
+ cris_ver_v32p,
+ cris_reg_mode_jump_op},
+
{"jump", 0x09b0, 0xF640, "r", 0, SIZE_NONE, 0,
cris_reg_mode_jump_op},
{"jump",
- JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "s", 0, SIZE_FIX_32, 0,
+ JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "s", 0, SIZE_FIX_32,
+ cris_ver_v0_10,
+ cris_none_reg_mode_jump_op},
+
+ {"jump",
+ JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "S", 0, SIZE_NONE,
+ cris_ver_v0_10,
+ cris_none_reg_mode_jump_op},
+
+ {"jump", 0x09F0, 0x060F, "P", 0, SIZE_NONE,
+ cris_ver_v32p,
cris_none_reg_mode_jump_op},
{"jump",
- JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "S", 0, SIZE_NONE, 0,
+ JUMP_PC_INCR_OPCODE_V32,
+ (0xffff & ~JUMP_PC_INCR_OPCODE_V32), "N", 0, SIZE_FIX_32,
+ cris_ver_v32p,
cris_none_reg_mode_jump_op},
{"jmpu", 0x8930, 0x72c0, "s", 0, SIZE_FIX_32,
- cris_ver_v10p,
+ cris_ver_v10,
cris_none_reg_mode_jump_op},
{"jmpu", 0x8930, 0x72c0, "S", 0, SIZE_NONE,
- cris_ver_v10p,
+ cris_ver_v10,
cris_none_reg_mode_jump_op},
+ {"lapc", 0x0970, 0x0680, "U,R", 0, SIZE_NONE,
+ cris_ver_v32p,
+ cris_not_implemented_op},
+
+ {"lapc", 0x0D7F, 0x0280, "dn,R", 0, SIZE_FIX_32,
+ cris_ver_v32p,
+ cris_not_implemented_op},
+
+ {"lapcq", 0x0970, 0x0680, "u,R", 0, SIZE_NONE,
+ cris_ver_v32p,
+ cris_addi_op},
+
{"lsl", 0x04C0, 0x0B00, "m r,R", 0, SIZE_NONE, 0,
cris_dstep_logshift_mstep_neg_not_op},
cris_ver_v3p,
cris_not_implemented_op},
+ {"mcp", 0x07f0, 0x0800, "P,r", 0, SIZE_NONE,
+ cris_ver_v32p,
+ cris_not_implemented_op},
+
{"move", 0x0640, 0x0980, "m r,R", 0, SIZE_NONE, 0,
cris_reg_mode_add_sub_cmp_and_or_move_op},
+ {"move", 0x0A40, 0x0180, "m s,R", 0, SIZE_FIELD, 0,
+ cris_none_reg_mode_add_sub_cmp_and_or_move_op},
+
+ {"move", 0x0A40, 0x0180, "m S,D", 0, SIZE_NONE,
+ cris_ver_v0_10,
+ cris_none_reg_mode_add_sub_cmp_and_or_move_op},
+
{"move", 0x0630, 0x09c0, "r,P", 0, SIZE_NONE, 0,
cris_move_to_preg_op},
{"move", 0x0BC0, 0x0000, "m R,y", 0, SIZE_FIELD, 0,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"move", 0x0BC0, 0x0000, "m D,S", 0, SIZE_NONE, 0,
- cris_none_reg_mode_add_sub_cmp_and_or_move_op},
-
- {"move", 0x0A40, 0x0180, "m s,R", 0, SIZE_FIELD, 0,
- cris_none_reg_mode_add_sub_cmp_and_or_move_op},
-
- {"move", 0x0A40, 0x0180, "m S,D", 0, SIZE_NONE, 0,
+ {"move", 0x0BC0, 0x0000, "m D,S", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
{"move", 0x0A30, 0x01c0, "s,P", 0, SIZE_SPEC_REG, 0,
cris_move_to_preg_op},
- {"move", 0x0A30, 0x01c0, "S,P", 0, SIZE_NONE, 0,
+ {"move", 0x0A30, 0x01c0, "S,P", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_move_to_preg_op},
{"move", 0x0A70, 0x0180, "P,y", 0, SIZE_SPEC_REG, 0,
cris_none_reg_mode_move_from_preg_op},
- {"move", 0x0A70, 0x0180, "P,S", 0, SIZE_NONE, 0,
+ {"move", 0x0A70, 0x0180, "P,S", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_none_reg_mode_move_from_preg_op},
+ {"move", 0x0B70, 0x0480, "r,T", 0, SIZE_NONE,
+ cris_ver_v32p,
+ cris_not_implemented_op},
+
+ {"move", 0x0F70, 0x0080, "T,r", 0, SIZE_NONE,
+ cris_ver_v32p,
+ cris_not_implemented_op},
+
{"movem", 0x0BF0, 0x0000, "R,y", 0, SIZE_FIX_32, 0,
cris_move_reg_to_mem_movem_op},
- {"movem", 0x0BF0, 0x0000, "D,S", 0, SIZE_NONE, 0,
+ {"movem", 0x0BF0, 0x0000, "D,S", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_move_reg_to_mem_movem_op},
{"movem", 0x0BB0, 0x0040, "s,R", 0, SIZE_FIX_32, 0,
cris_move_mem_to_reg_movem_op},
- {"movem", 0x0BB0, 0x0040, "S,D", 0, SIZE_NONE, 0,
+ {"movem", 0x0BB0, 0x0040, "S,D", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_move_mem_to_reg_movem_op},
{"moveq", 0x0240, 0x0D80, "i,R", 0, SIZE_NONE, 0,
{"movs", 0x0460, 0x0B80, "z r,R", 0, SIZE_NONE, 0,
cris_reg_mode_add_sub_cmp_and_or_move_op},
+ /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
{"movs", 0x0860, 0x0380, "z s,R", 0, SIZE_FIELD, 0,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"movs", 0x0860, 0x0380, "z S,D", 0, SIZE_NONE, 0,
+ {"movs", 0x0860, 0x0380, "z S,D", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
{"movu", 0x0440, 0x0Ba0, "z r,R", 0, SIZE_NONE, 0,
cris_reg_mode_add_sub_cmp_and_or_move_op},
+ /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
{"movu", 0x0840, 0x03a0, "z s,R", 0, SIZE_FIELD, 0,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"movu", 0x0840, 0x03a0, "z S,D", 0, SIZE_NONE, 0,
+ {"movu", 0x0840, 0x03a0, "z S,D", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"mstep", 0x07f0, 0x0800, "r,R", 0, SIZE_NONE, 0,
+ {"mstep", 0x07f0, 0x0800, "r,R", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_dstep_logshift_mstep_neg_not_op},
{"muls", 0x0d00, 0x02c0, "m r,R", 0, SIZE_NONE,
{"neg", 0x0580, 0x0A40, "m r,R", 0, SIZE_NONE, 0,
cris_dstep_logshift_mstep_neg_not_op},
- {"nop", NOP_OPCODE, NOP_Z_BITS, "", 0, SIZE_NONE, 0,
+ {"nop", NOP_OPCODE, NOP_Z_BITS, "", 0, SIZE_NONE,
+ cris_ver_v0_10,
+ cris_btst_nop_op},
+
+ {"nop", NOP_OPCODE_V32, NOP_Z_BITS_V32, "", 0, SIZE_NONE,
+ cris_ver_v32p,
cris_btst_nop_op},
{"not", 0x8770, 0x7880, "r", 0, SIZE_NONE, 0,
{"or", 0x0B40, 0x0080, "m s,R", 0, SIZE_FIELD, 0,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"or", 0x0B40, 0x0080, "m S,D", 0, SIZE_NONE, 0,
+ {"or", 0x0B40, 0x0080, "m S,D", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"or", 0x0B40, 0x0480, "m S,R,r", 0, SIZE_NONE, 0,
+ {"or", 0x0B40, 0x0480, "m S,R,r", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_three_operand_add_sub_cmp_and_or_op},
{"orq", 0x0340, 0x0C80, "i,R", 0, SIZE_NONE, 0,
cris_quick_mode_and_cmp_move_or_op},
- {"pop", 0x0E6E, 0x0191, "!R", 0, SIZE_NONE, 0,
+ {"pop", 0x0E6E, 0x0191, "!R", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"pop", 0x0e3e, 0x01c1, "!P", 0, SIZE_NONE, 0,
+ {"pop", 0x0e3e, 0x01c1, "!P", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_none_reg_mode_move_from_preg_op},
- {"push", 0x0FEE, 0x0011, "BR", 0, SIZE_NONE, 0,
+ {"push", 0x0FEE, 0x0011, "BR", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"push", 0x0E7E, 0x0181, "BP", 0, SIZE_NONE, 0,
+ {"push", 0x0E7E, 0x0181, "BP", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_move_to_preg_op},
{"rbf", 0x3b30, 0xc0c0, "y", 0, SIZE_NONE,
- cris_ver_v10p,
+ cris_ver_v10,
cris_not_implemented_op},
{"rbf", 0x3b30, 0xc0c0, "S", 0, SIZE_NONE,
- cris_ver_v10p,
+ cris_ver_v10,
+ cris_not_implemented_op},
+
+ {"rfe", 0x2930, 0xD6CF, "", 0, SIZE_NONE,
+ cris_ver_v32p,
+ cris_not_implemented_op},
+
+ {"rfg", 0x4930, 0xB6CF, "", 0, SIZE_NONE,
+ cris_ver_v32p,
+ cris_not_implemented_op},
+
+ {"rfn", 0x5930, 0xA6CF, "", 0, SIZE_NONE,
+ cris_ver_v32p,
cris_not_implemented_op},
- {"ret", 0xB67F, 0x4980, "", 1, SIZE_NONE, 0,
+ {"ret", 0xB67F, 0x4980, "", 1, SIZE_NONE,
+ cris_ver_v0_10,
+ cris_reg_mode_move_from_preg_op},
+
+ {"ret", 0xB9F0, 0x460F, "", 1, SIZE_NONE,
+ cris_ver_v32p,
cris_reg_mode_move_from_preg_op},
- {"retb", 0xe67f, 0x1980, "", 1, SIZE_NONE, 0,
+ {"retb", 0xe67f, 0x1980, "", 1, SIZE_NONE,
+ cris_ver_v0_10,
cris_reg_mode_move_from_preg_op},
- {"reti", 0xA67F, 0x5980, "", 1, SIZE_NONE, 0,
+ {"rete", 0xA9F0, 0x560F, "", 1, SIZE_NONE,
+ cris_ver_v32p,
+ cris_reg_mode_move_from_preg_op},
+
+ {"reti", 0xA67F, 0x5980, "", 1, SIZE_NONE,
+ cris_ver_v0_10,
+ cris_reg_mode_move_from_preg_op},
+
+ {"retn", 0xC9F0, 0x360F, "", 1, SIZE_NONE,
+ cris_ver_v32p,
cris_reg_mode_move_from_preg_op},
{"sbfs", 0x3b70, 0xc080, "y", 0, SIZE_NONE,
- cris_ver_v10p,
+ cris_ver_v10,
cris_not_implemented_op},
{"sbfs", 0x3b70, 0xc080, "S", 0, SIZE_NONE,
- cris_ver_v10p,
+ cris_ver_v10,
cris_not_implemented_op},
{"sa",
0x0AC0+(0xf-CC_A)*0x1000, "r", 0, SIZE_NONE, 0,
cris_scc_op},
+ {"ssb",
+ 0x0530+CC_EXT*0x1000,
+ 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
+ cris_ver_v32p,
+ cris_scc_op},
+
{"scc",
0x0530+CC_CC*0x1000,
0x0AC0+(0xf-CC_CC)*0x1000, "r", 0, SIZE_NONE, 0,
{"setf", 0x05b0, 0x0A40, "f", 0, SIZE_NONE, 0,
cris_ax_ei_setf_op},
+ {"sfe", 0x3930, 0xC6CF, "", 0, SIZE_NONE,
+ cris_ver_v32p,
+ cris_not_implemented_op},
+
/* Need to have "swf" in front of "sext" so it is the one displayed in
disassembly. */
{"swf",
0x0530+CC_EXT*0x1000,
0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
- cris_ver_v10p,
+ cris_ver_v10,
cris_scc_op},
{"sext",
{"sub", 0x0a80, 0x0140, "m s,R", 0, SIZE_FIELD, 0,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"sub", 0x0a80, 0x0140, "m S,D", 0, SIZE_NONE, 0,
+ {"sub", 0x0a80, 0x0140, "m S,D", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"sub", 0x0a80, 0x0540, "m S,R,r", 0, SIZE_NONE, 0,
+ {"sub", 0x0a80, 0x0540, "m S,R,r", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_three_operand_add_sub_cmp_and_or_op},
{"subq", 0x0280, 0x0d40, "I,R", 0, SIZE_NONE, 0,
{"subs", 0x04a0, 0x0b40, "z r,R", 0, SIZE_NONE, 0,
cris_reg_mode_add_sub_cmp_and_or_move_op},
+ /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
{"subs", 0x08a0, 0x0340, "z s,R", 0, SIZE_FIELD, 0,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"subs", 0x08a0, 0x0340, "z S,D", 0, SIZE_NONE, 0,
+ {"subs", 0x08a0, 0x0340, "z S,D", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"subs", 0x08a0, 0x0740, "z S,R,r", 0, SIZE_NONE, 0,
+ {"subs", 0x08a0, 0x0740, "z S,R,r", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_three_operand_add_sub_cmp_and_or_op},
{"subu", 0x0480, 0x0b60, "z r,R", 0, SIZE_NONE, 0,
cris_reg_mode_add_sub_cmp_and_or_move_op},
+ /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
{"subu", 0x0880, 0x0360, "z s,R", 0, SIZE_FIELD, 0,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"subu", 0x0880, 0x0360, "z S,D", 0, SIZE_NONE, 0,
+ {"subu", 0x0880, 0x0360, "z S,D", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
- {"subu", 0x0880, 0x0760, "z S,R,r", 0, SIZE_NONE, 0,
+ {"subu", 0x0880, 0x0760, "z S,R,r", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_three_operand_add_sub_cmp_and_or_op},
{"svc",
cris_ver_v8p,
cris_not_implemented_op},
- {"test", 0x0640, 0x0980, "m D", 0, SIZE_NONE, 0,
+ {"test", 0x0640, 0x0980, "m D", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_reg_mode_test_op},
- {"test", 0x0b80, 0xf040, "m s", 0, SIZE_FIELD, 0,
+ {"test", 0x0b80, 0xf040, "m y", 0, SIZE_FIELD, 0,
cris_none_reg_mode_clear_test_op},
- {"test", 0x0b80, 0xf040, "m S", 0, SIZE_NONE, 0,
+ {"test", 0x0b80, 0xf040, "m S", 0, SIZE_NONE,
+ cris_ver_v0_10,
cris_none_reg_mode_clear_test_op},
{"xor", 0x07B0, 0x0840, "r,R", 0, SIZE_NONE, 0,
"gt",
"le",
"a",
- /* In v0, this would be "ext". */
- "wf",
+ /* This is a placeholder. In v0, this would be "ext". In v32, this
+ is "sb". See cris_conds15. */
+ "wf"
+};
+
+/* Different names and semantics for condition 1111 (0xf). */
+const struct cris_cond15 cris_cond15s[] =
+{
+ /* FIXME: In what version did condition "ext" disappear? */
+ {"ext", cris_ver_v0_3},
+ {"wf", cris_ver_v10},
+ {"sb", cris_ver_v32p},
+ {NULL, 0}
};
projects / external / binutils.git / commitdiff