radeonsi/gfx9: add radeon_surf.gfx9.surf_offset

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index f1b2cd9..2e66dd0 100644 (file)
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -555,7 +555,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
        }
 
        if (rscreen->chip_class >= GFX9) {
-               offset = 0;
+               offset = rtex->surface.u.gfx9.surf_offset;
                stride = rtex->surface.u.gfx9.surf_pitch *
                         rtex->surface.bpe;
                slice_size = rtex->surface.u.gfx9.surf_slice_size;

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 5b032bf..b3c7608 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -354,6 +354,7 @@ struct gfx9_surf_layout {
     struct gfx9_surf_meta_flags cmask; /* metadata of fmask */
 
     enum gfx9_resource_type     resource_type; /* 1D, 2D or 3D */
+    uint64_t                    surf_offset; /* 0 unless imported with an offset */
     /* The size of the 2D plane containing all mipmap levels. */
     uint64_t                    surf_slice_size;
     uint16_t                    surf_pitch; /* in blocks */

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 58d35da..fb82f8f 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -398,6 +398,8 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
                /* Only stencil_offset needs to be added here. */
                if (is_stencil)
                        va += tex->surface.u.gfx9.stencil_offset;
+               else
+                       va += tex->surface.u.gfx9.surf_offset;
        } else {
                va += base_level_info->offset;
        }

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index de64e64..c4063a8 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2271,6 +2271,7 @@ static void si_init_depth_surface(struct si_context *sctx,
        surf->db_htile_surface = 0;
 
        if (sctx->b.chip_class >= GFX9) {
+               assert(rtex->surface.u.gfx9.surf_offset == 0);
                surf->db_depth_base = rtex->resource.gpu_address >> 8;
                surf->db_stencil_base = (rtex->resource.gpu_address +
                                         rtex->surface.u.gfx9.stencil_offset) >> 8;
@@ -2658,6 +2659,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
                                meta = tex->surface.u.gfx9.cmask;
 
                        /* Set mutable surface parameters. */
+                       cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
                        cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
                                           S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
                                           S_028C74_RB_ALIGNED(meta.rb_aligned) |

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index dd3a154..fd9e4dd 100644 (file)
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -902,6 +902,7 @@ static int gfx9_surface_init(struct radeon_winsys *rws,
    surf->surf_size = 0;
    surf->dcc_size = 0;
    surf->htile_size = 0;
+   surf->u.gfx9.surf_offset = 0;
    surf->u.gfx9.stencil_offset = 0;
    surf->u.gfx9.fmask_size = 0;
    surf->u.gfx9.cmask_size = 0;