void addPreRegAlloc() override;
void addPreSched2() override;
void addPreEmitPass() override;
+ void addPreEmitPass2() override;
std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
};
// Don't optimize barriers at -O0.
if (getOptLevel() != CodeGenOpt::None)
addPass(createARMOptimizeBarriersPass());
+}
+void ARMPassConfig::addPreEmitPass2() {
addPass(createARMConstantIslandPass());
addPass(createARMLowOverheadLoopsPass());
; CHECK-NEXT: Thumb2 instruction size reduce pass
; CHECK-NEXT: Unpack machine instruction bundles
; CHECK-NEXT: optimise barriers pass
+; CHECK-NEXT: Contiguously Lay Out Funclets
+; CHECK-NEXT: StackMap Liveness Analysis
+; CHECK-NEXT: Live DEBUG_VALUE analysis
; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: ARM constant island placement and branch shortening pass
; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: Machine Natural Loop Construction
; CHECK-NEXT: ReachingDefAnalysis
; CHECK-NEXT: ARM Low Overhead Loops pass
-; CHECK-NEXT: Contiguously Lay Out Funclets
-; CHECK-NEXT: StackMap Liveness Analysis
-; CHECK-NEXT: Live DEBUG_VALUE analysis
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
; CHECK-NEXT: ARM Assembly Printer
---
name: _ZN1BC2Ev
alignment: 2
+tracksRegLiveness: true
liveins:
- { reg: '$r0' }
frameInfo:
callee-saved-register: '$r4' }
body: |
bb.0.entry:
+ liveins: $r0, $r4, $lr
+
frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4
---
name: _ZN1BC1Ev
alignment: 2
+tracksRegLiveness: true
liveins:
- { reg: '$r0' }
frameInfo:
callee-saved-register: '$r4' }
body: |
bb.0.entry:
+ liveins: $r0, $r4, $lr
+
frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4
!13 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !14)
!14 = !DICompositeType(tag: DW_TAG_structure_type, name: "CGRect", scope: !5, file: !3, line: 46, size: 128, elements: !4, runtimeLang: DW_LANG_Swift, identifier: "$sSo6CGRectVD")
name: 'f'
+tracksRegLiveness: true
body: |
bb.0:
+ liveins: $r6
+
DBG_VALUE $s31, $noreg, !12, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !10
DBG_VALUE $q8, $noreg, !12, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !10
renamable $r0 = t2ADDri $r6, 144, 14, $noreg, $noreg, debug-location !10
...
---
name: fn1
-tracksRegLiveness: false
+tracksRegLiveness: true
body: |
bb.0.entry:
+ liveins: $r0, $r1, $r4, $lr
+
$sp = frame-setup STMDB_UPD $sp, 14, $noreg, killed $r4, killed $lr
$r4 = MOVr $r0, 14, $noreg, $noreg
DBG_VALUE $r1, $noreg, !17, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !18
!9 = !DILocalVariable(name: "q9", scope: !5, file: !4, line: 1, type: !7)
!20 = !DILocation(line: 0, scope: !5)
name: f
+tracksRegLiveness: true
body: |
bb.2.for.body:
+ liveins: $r2
+
+ t2CMPri killed renamable $r2, 5, 14, $noreg, implicit-def $cpsr
t2Bcc %bb.2.for.body, 0, killed $cpsr, debug-location !20
DBG_VALUE $q8, $noreg, !8, !DIExpression(DW_OP_LLVM_fragment, 0, 64), debug-location !20
DBG_VALUE $q9, $noreg, !9, !DIExpression(DW_OP_LLVM_fragment, 0, 56), debug-location !20