clk: starfive: Keep the clock apb0 enabled always

This solves crush problem of i2c runtime pm and
prevents some aon modules from working abnormally.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index 2b02740a07a601a297bdf3048351258dc5af44f7..7b52a6145e55b4dd734a20916e4111178bbf2c90 100644 (file)
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -50,7 +50,7 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
        JH7110_GATE(JH7110_AHB1, "ahb1", CLK_IS_CRITICAL, JH7110_STG_AXIAHB),
        JH7110__DIV(JH7110_APB_BUS_FUNC, "apb_bus_func",
                        8, JH7110_STG_AXIAHB),
-       JH7110_GATE(JH7110_APB0, "apb0", CLK_IGNORE_UNUSED, JH7110_APB_BUS),
+       JH7110_GATE(JH7110_APB0, "apb0", CLK_IS_CRITICAL, JH7110_APB_BUS),
        JH7110__DIV(JH7110_PLL0_DIV2, "pll0_div2", 2, JH7110_PLL0_OUT),
        JH7110__DIV(JH7110_PLL1_DIV2, "pll1_div2", 2, JH7110_PLL1_OUT),
        JH7110__DIV(JH7110_PLL2_DIV2, "pll2_div2", 2, JH7110_PLL2_OUT),