typedef intmax_t atomic_max_t;
typedef uintmax_t uatomic_max_t;
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 1
/* Compare and exchange.
For all "bool" routines, we return FALSE if exchange succesful. */
typedef intmax_t atomic_max_t;
typedef uintmax_t uatomic_max_t;
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
#ifdef UP
# define __MB /* nothing */
typedef intmax_t atomic_max_t;
typedef uintmax_t uatomic_max_t;
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
void __arm_link_error (void);
#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
# endif
#endif
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
__sync_val_compare_and_swap (mem, oldval, newval)
typedef intmax_t atomic_max_t;
typedef uintmax_t uatomic_max_t;
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
#define __arch_compare_and_exchange_bool_8_acq(mem, newval, oldval) \
(abort (), 0)
typedef intmax_t atomic_max_t;
typedef uintmax_t uatomic_max_t;
+/* If we have just non-atomic operations, we can as well make them wide. */
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
/* The only basic operation needed is compare and exchange. */
#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
({ __typeof (mem) __gmemp = (mem); \
typedef intmax_t atomic_max_t;
typedef uintmax_t uatomic_max_t;
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
({ __typeof (*(mem)) __ret; \
__asm __volatile ("cas%.b %0,%2,%1" \
typedef intmax_t atomic_max_t;
typedef uintmax_t uatomic_max_t;
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
/* Microblaze does not have byte and halfword forms of load and reserve and
store conditional. So for microblaze we stub out the 8- and 16-bit forms. */
#define MIPS_PUSH_MIPS2
#endif
+#if _MIPS_SIM == _ABIO32
+#define __HAVE_64B_ATOMICS 0
+#else
+#define __HAVE_64B_ATOMICS 1
+#endif
+
/* See the comments in <sys/asm.h> about the use of the sync instruction. */
#ifndef MIPS_SYNC
# define MIPS_SYNC sync
have no assembly alternative available and want to avoid the __sync_*
builtins if at all possible. */
+#define USE_ATOMIC_COMPILER_BUILTINS 1
+
/* Compare and exchange.
For all "bool" routines, we return FALSE if exchange succesful. */
/* This implementation using inline assembly will be removed once glibc
requires GCC 4.8 or later to build. */
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
/* Compare and exchange. For all of the "xxx" routines, we expect a
"__prev" and a "__cmp" variable to be provided by the enclosing scope,
in which values are returned. */
# define MUTEX_HINT_REL
#endif
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
/*
* The 32-bit exchange_bool is different on powerpc64 because the subf
* does signed 64-bit arithmetic while the lwarx is 32-bit unsigned
# define MUTEX_HINT_REL
#endif
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
/* The 32-bit exchange_bool is different on powerpc64 because the subf
does signed 64-bit arithmetic while the lwarx is 32-bit unsigned
(a load word and zero (high 32) form) load.
typedef intmax_t atomic_max_t;
typedef uintmax_t uatomic_max_t;
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
(abort (), (__typeof (*mem)) 0)
__archold; })
#ifdef __s390x__
+# define __HAVE_64B_ATOMICS 1
# define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
({ __typeof (mem) __archmem = (mem); \
__typeof (*mem) __archold = (oldval); \
: "d" ((long) (newval)), "m" (*__archmem) : "cc", "memory" ); \
__archold; })
#else
+# define __HAVE_64B_ATOMICS 0
/* For 31 bit we do not really need 64-bit compare-and-exchange. We can
implement them by use of the csd instruction. The straightforward
implementation causes warnings so we skip the definition for now. */
typedef intmax_t atomic_max_t;
typedef uintmax_t uatomic_max_t;
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
/* We have no compare and swap, just test and set.
The following implementation contends on 64 global locks
typedef intmax_t atomic_max_t;
typedef uintmax_t uatomic_max_t;
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
(abort (), (__typeof (*mem)) 0)
typedef intmax_t atomic_max_t;
typedef uintmax_t uatomic_max_t;
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
(abort (), (__typeof (*mem)) 0)
#include <arch/spr_def.h>
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
/* Pick appropriate 8- or 4-byte instruction. */
#define __atomic_update(mem, v, op) \
((__typeof (*(mem))) (__typeof (*(mem) - *(mem))) \
#include <asm/unistd.h>
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
/* 32-bit integer compare-and-exchange. */
static __inline __attribute__ ((always_inline))
int __atomic_cmpxchg_32 (volatile int *mem, int newval, int oldval)
typedef intmax_t atomic_max_t;
typedef uintmax_t uatomic_max_t;
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
/* prev = *addr;
if (prev == old)
*addr = new;
typedef intmax_t atomic_max_t;
typedef uintmax_t uatomic_max_t;
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
/* The only basic operation needed is compare and exchange. */
/* For ColdFire we'll have to trap into the kernel mode anyway,
so trap from the library rather then from the kernel wrapper. */
typedef intmax_t atomic_max_t;
typedef uintmax_t uatomic_max_t;
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
/* SH kernel has implemented a gUSA ("g" User Space Atomicity) support
for the user space atomicity. The atomicity macros use this scheme.
# endif
#endif
+#define __HAVE_64B_ATOMICS 1
+#if __GNUC_PREREQ (4, 7)
+#define USE_ATOMIC_COMPILER_BUILTINS 1
+#else
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+#endif
#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
__sync_val_compare_and_swap (mem, oldval, newval)