{
int ret;
- spi_nor_write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
ret = macronix_set_4byte(nor, enable);
- spi_nor_write_disable(nor);
+ if (ret)
+ return ret;
- return ret;
+ return spi_nor_write_disable(nor);
}
static int spansion_set_4byte(struct spi_nor *nor, bool enable)
* Register to be set to 1, so all 3-byte-address reads come from the
* second 16M. We must clear the register to enable normal behavior.
*/
- spi_nor_write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
ret = spi_nor_write_ear(nor, 0);
- spi_nor_write_disable(nor);
+ if (ret)
+ return ret;
- return ret;
+ return spi_nor_write_disable(nor);
}
static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
{
int ret;
- spi_nor_write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
if (nor->spimem) {
struct spi_mem_op op =
{
int ret;
- spi_nor_write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
ret = spi_nor_write_sr(nor, status_new);
if (ret)
return ret;
list_for_each_entry_safe(cmd, next, &erase_list, list) {
nor->erase_opcode = cmd->opcode;
while (cmd->count) {
- spi_nor_write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto destroy_erase_cmd_list;
ret = spi_nor_erase_sector(nor, addr);
if (ret)
if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
unsigned long timeout;
- spi_nor_write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto erase_err;
ret = spi_nor_erase_chip(nor);
if (ret)
/* "sector"-at-a-time erase */
} else if (spi_nor_has_uniform_erase(nor)) {
while (len) {
- spi_nor_write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto erase_err;
ret = spi_nor_erase_sector(nor, addr);
if (ret)
goto erase_err;
}
- spi_nor_write_disable(nor);
+ ret = spi_nor_write_disable(nor);
erase_err:
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
if (nor->bouncebuf[0] & SR_QUAD_EN_MX)
return 0;
- spi_nor_write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
- spi_nor_write_sr(nor, nor->bouncebuf[0] | SR_QUAD_EN_MX);
+ ret = spi_nor_write_sr(nor, nor->bouncebuf[0] | SR_QUAD_EN_MX);
+ if (ret)
+ return ret;
ret = spi_nor_wait_till_ready(nor);
if (ret)
/* Update the Quad Enable bit. */
*sr2 |= SR2_QUAD_EN_BIT7;
- spi_nor_write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
ret = spi_nor_write_sr2(nor, sr2);
if (ret)
if (ret)
return ret;
- spi_nor_write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
ret = spi_nor_write_sr(nor, nor->bouncebuf[0] & ~mask);
if (ret)
if (ret)
return ret;
- spi_nor_write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto sst_write_err;
nor->sst_write_second = false;
}
nor->sst_write_second = false;
- spi_nor_write_disable(nor);
+ ret = spi_nor_write_disable(nor);
+ if (ret)
+ goto sst_write_err;
+
ret = spi_nor_wait_till_ready(nor);
if (ret)
goto sst_write_err;
/* Write out trailing byte if it exists. */
if (actual != len) {
- spi_nor_write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto sst_write_err;
nor->program_opcode = SPINOR_OP_BP;
ret = spi_nor_write_data(nor, to, 1, buf + actual);
ret = spi_nor_wait_till_ready(nor);
if (ret)
goto sst_write_err;
- spi_nor_write_disable(nor);
+
actual += 1;
+
+ ret = spi_nor_write_disable(nor);
}
sst_write_err:
*retlen += actual;
addr = spi_nor_convert_addr(nor, addr);
- spi_nor_write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto write_err;
+
ret = spi_nor_write_data(nor, addr, page_remain, buf + i);
if (ret < 0)
goto write_err;