drm/i915: simplify the reduced clock handling for pch plls

Just move the lowfreq_avail logic out of the register writing as a
prep step for the next patch, which will coalesce all the pch pll
enabling into one spot.

Note that writing the reduced clock dividers to FP1 in a few more
cases (as this patch ends up doing) isn't really relevant since the
FP1 value only matters when we enable the low lock. Which despite
can only happen if we've actually enabled the reduced dotclock and
furthermore isn't even properly implemented on ilk+: Despite claims to
the contrary in the code switching between frequencies if fully
manual.

v2: Explain matters around the FP1 change to answer a question Damien
raised in his review.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d617a72..b23937b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5730,7 +5730,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
                if (encoder->pre_pll_enable)
                        encoder->pre_pll_enable(encoder);
 
-       intel_crtc->lowfreq_avail = false;
+       if (is_lvds && has_reduced_clock && i915_powersave)
+               intel_crtc->lowfreq_avail = true;
+       else
+               intel_crtc->lowfreq_avail = false;
 
        if (intel_crtc->config.has_pch_encoder) {
                pll = intel_crtc_to_shared_dpll(intel_crtc);
@@ -5748,12 +5751,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
                 */
                I915_WRITE(PCH_DPLL(pll->id), dpll);
 
-               if (is_lvds && has_reduced_clock && i915_powersave) {
+               if (has_reduced_clock)
                        I915_WRITE(PCH_FP1(pll->id), fp2);
-                       intel_crtc->lowfreq_avail = true;
-               } else {
+               else
                        I915_WRITE(PCH_FP1(pll->id), fp);
-               }
        }
 
        intel_set_pipe_timings(intel_crtc);