namespace llvm {
namespace mca {
+class LSUnit;
class RegisterFile;
struct StallInfo {
REGISTER_DEPS,
DISPATCH,
DELAY,
+ LOAD_STORE,
CUSTOM_STALL
};
RegisterFile &PRF;
ResourceManager RM;
CustomBehaviour &CB;
+ LSUnit &LSU;
/// Instructions that were issued, but not executed yet.
SmallVector<InstRef, 4> IssuedInst;
public:
InOrderIssueStage(const MCSubtargetInfo &STI, RegisterFile &PRF,
- CustomBehaviour &CB);
+ CustomBehaviour &CB, LSUnit &LSU);
unsigned getIssueWidth() const;
bool isAvailable(const InstRef &) const override;
CustomBehaviour &CB) {
const MCSchedModel &SM = STI.getSchedModel();
auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
+ auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
+ Opts.StoreQueueSize, Opts.AssumeNoAlias);
// Create the pipeline stages.
auto Entry = std::make_unique<EntryStage>(SrcMgr);
- auto InOrderIssue = std::make_unique<InOrderIssueStage>(STI, *PRF, CB);
+ auto InOrderIssue = std::make_unique<InOrderIssueStage>(STI, *PRF, CB, *LSU);
auto StagePipeline = std::make_unique<Pipeline>();
// Pass the ownership of all the hardware units to this Context.
addHardwareUnit(std::move(PRF));
+ addHardwareUnit(std::move(LSU));
// Build the pipeline.
StagePipeline->appendStage(std::move(Entry));
//===----------------------------------------------------------------------===//
#include "llvm/MCA/Stages/InOrderIssueStage.h"
+#include "llvm/MCA/HardwareUnits/LSUnit.h"
#include "llvm/MCA/HardwareUnits/RegisterFile.h"
#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
#include "llvm/MCA/Instruction.h"
}
InOrderIssueStage::InOrderIssueStage(const MCSubtargetInfo &STI,
- RegisterFile &PRF, CustomBehaviour &CB)
- : STI(STI), PRF(PRF), RM(STI.getSchedModel()), CB(CB), NumIssued(), SI(),
- CarryOver(), Bandwidth(), LastWriteBackCycle() {}
+ RegisterFile &PRF, CustomBehaviour &CB,
+ LSUnit &LSU)
+ : STI(STI), PRF(PRF), RM(STI.getSchedModel()), CB(CB), LSU(LSU),
+ NumIssued(), SI(), CarryOver(), Bandwidth(), LastWriteBackCycle() {}
unsigned InOrderIssueStage::getIssueWidth() const {
return STI.getSchedModel().IssueWidth;
return false;
}
+ if (IR.getInstruction()->isMemOp() && !LSU.isReady(IR)) {
+ // This load (store) aliases with a preceding store (load). Delay
+ // it until the depenency is cleared.
+ SI.update(IR, /* delay */ 1, StallInfo::StallKind::LOAD_STORE);
+ return false;
+ }
+
if (unsigned CustomStallCycles = CB.checkCustomHazard(IssuedInst, IR)) {
SI.update(IR, CustomStallCycles, StallInfo::StallKind::CUSTOM_STALL);
return false;
}
llvm::Error InOrderIssueStage::execute(InstRef &IR) {
+ Instruction &IS = *IR.getInstruction();
+ if (IS.isMemOp())
+ IS.setLSUTokenID(LSU.dispatch(IR));
+
if (llvm::Error E = tryIssue(IR))
return E;
RM.issueInstruction(Desc, UsedResources);
IS.execute(SourceIndex);
+ if (IS.isMemOp())
+ LSU.onInstructionIssued(IR);
+
// Replace resource masks with valid resource processor IDs.
for (ResourceUse &Use : UsedResources) {
uint64_t Mask = Use.first.first;
}
PRF.onInstructionExecuted(&IS);
+ LSU.onInstructionExecuted(IR);
notifyInstructionExecuted(IR);
++NumExecuted;
for (const WriteState &WS : IS.getDefs())
PRF.removeRegisterWrite(WS, FreedRegs);
+ if (IS.isMemOp())
+ LSU.onInstructionRetired(IR);
+
notifyInstructionRetired(IR, FreedRegs);
}
Bandwidth = getIssueWidth();
PRF.cycleStart();
+ LSU.cycleEvent();
// Release consumed resources.
SmallVector<ResourceRef, 4> Freed;
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 -timeline --iterations=5 -noalias=false < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 -timeline --iterations=3 -noalias=false < %s | FileCheck %s
# PR50483: Execution of loads and stores should not overlap if flag -noalias is set to false.
-str x1, [x4]
-ldr x2, [x4]
+str x1, [x10]
+str x1, [x10]
+ldr x2, [x10]
+nop
+ldr x2, [x10]
+ldr x3, [x10]
-# CHECK: Iterations: 5
-# CHECK-NEXT: Instructions: 10
-# CHECK-NEXT: Total Cycles: 8
-# CHECK-NEXT: Total uOps: 10
+# CHECK: Iterations: 3
+# CHECK-NEXT: Instructions: 18
+# CHECK-NEXT: Total Cycles: 31
+# CHECK-NEXT: Total uOps: 18
# CHECK: Dispatch Width: 2
-# CHECK-NEXT: uOps Per Cycle: 1.25
-# CHECK-NEXT: IPC: 1.25
-# CHECK-NEXT: Block RThroughput: 1.0
+# CHECK-NEXT: uOps Per Cycle: 0.58
+# CHECK-NEXT: IPC: 0.58
+# CHECK-NEXT: Block RThroughput: 3.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 * str x1, [x4]
-# CHECK-NEXT: 1 3 1.00 * ldr x2, [x4]
+# CHECK-NEXT: 1 1 1.00 * str x1, [x10]
+# CHECK-NEXT: 1 1 1.00 * str x1, [x10]
+# CHECK-NEXT: 1 3 1.00 * ldr x2, [x10]
+# CHECK-NEXT: 1 1 1.00 * * U nop
+# CHECK-NEXT: 1 3 1.00 * ldr x2, [x10]
+# CHECK-NEXT: 1 3 1.00 * ldr x3, [x10]
# CHECK: Resources:
# CHECK-NEXT: [0.0] - CortexA55UnitALU
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8]
-# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00
+# CHECK-NEXT: - - 1.00 - - - - - - 3.00 - 2.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8] Instructions:
-# CHECK-NEXT: - - - - - - - - - - - 1.00 str x1, [x4]
-# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr x2, [x4]
+# CHECK-NEXT: - - - - - - - - - - - 1.00 str x1, [x10]
+# CHECK-NEXT: - - - - - - - - - - - 1.00 str x1, [x10]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr x2, [x10]
+# CHECK-NEXT: - - 1.00 - - - - - - - - - nop
+# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr x2, [x10]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr x3, [x10]
# CHECK: Timeline view:
-# CHECK-NEXT: Index 01234567
+# CHECK-NEXT: 0123456789 0
+# CHECK-NEXT: Index 0123456789 0123456789
-# CHECK: [0,0] DE . . str x1, [x4]
-# CHECK-NEXT: [0,1] DeeE . . ldr x2, [x4]
-# CHECK-NEXT: [1,0] .DE . . str x1, [x4]
-# CHECK-NEXT: [1,1] .DeeE. . ldr x2, [x4]
-# CHECK-NEXT: [2,0] . DE . . str x1, [x4]
-# CHECK-NEXT: [2,1] . DeeE . ldr x2, [x4]
-# CHECK-NEXT: [3,0] . DE. . str x1, [x4]
-# CHECK-NEXT: [3,1] . DeeE. ldr x2, [x4]
-# CHECK-NEXT: [4,0] . DE . str x1, [x4]
-# CHECK-NEXT: [4,1] . DeeE ldr x2, [x4]
+# CHECK: [0,0] DE . . . . . . str x1, [x10]
+# CHECK-NEXT: [0,1] .DE . . . . . . str x1, [x10]
+# CHECK-NEXT: [0,2] . DeeE . . . . . ldr x2, [x10]
+# CHECK-NEXT: [0,3] . DE . . . . . nop
+# CHECK-NEXT: [0,4] . .DeeE. . . . . ldr x2, [x10]
+# CHECK-NEXT: [0,5] . . DeeE . . . . ldr x3, [x10]
+# CHECK-NEXT: [1,0] . . DE . . . . str x1, [x10]
+# CHECK-NEXT: [1,1] . . .DE . . . . str x1, [x10]
+# CHECK-NEXT: [1,2] . . . DeeE . . . ldr x2, [x10]
+# CHECK-NEXT: [1,3] . . . DE . . . nop
+# CHECK-NEXT: [1,4] . . . .DeeE. . . ldr x2, [x10]
+# CHECK-NEXT: [1,5] . . . . DeeE . . ldr x3, [x10]
+# CHECK-NEXT: [2,0] . . . . DE . . str x1, [x10]
+# CHECK-NEXT: [2,1] . . . . .DE . . str x1, [x10]
+# CHECK-NEXT: [2,2] . . . . . DeeE . ldr x2, [x10]
+# CHECK-NEXT: [2,3] . . . . . DE . nop
+# CHECK-NEXT: [2,4] . . . . . .DeeE. ldr x2, [x10]
+# CHECK-NEXT: [2,5] . . . . . . DeeE ldr x3, [x10]
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 5 0.0 0.0 0.0 str x1, [x4]
-# CHECK-NEXT: 1. 5 0.0 0.0 0.0 ldr x2, [x4]
-# CHECK-NEXT: 5 0.0 0.0 0.0 <total>
+# CHECK-NEXT: 0. 3 0.0 0.0 0.0 str x1, [x10]
+# CHECK-NEXT: 1. 3 0.0 0.0 0.0 str x1, [x10]
+# CHECK-NEXT: 2. 3 0.0 0.0 0.0 ldr x2, [x10]
+# CHECK-NEXT: 3. 3 0.0 0.0 0.0 nop
+# CHECK-NEXT: 4. 3 0.0 0.0 0.0 ldr x2, [x10]
+# CHECK-NEXT: 5. 3 0.0 0.0 0.0 ldr x3, [x10]
+# CHECK-NEXT: 3 0.0 0.0 0.0 <total>
--- /dev/null
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 -timeline --iterations=3 --noalias=true < %s | FileCheck %s
+
+str x1, [x10]
+str x1, [x10]
+ldr x2, [x10]
+nop
+ldr x2, [x10]
+ldr x3, [x10]
+
+# CHECK: Iterations: 3
+# CHECK-NEXT: Instructions: 18
+# CHECK-NEXT: Total Cycles: 19
+# CHECK-NEXT: Total uOps: 18
+
+# CHECK: Dispatch Width: 2
+# CHECK-NEXT: uOps Per Cycle: 0.95
+# CHECK-NEXT: IPC: 0.95
+# CHECK-NEXT: Block RThroughput: 3.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 * str x1, [x10]
+# CHECK-NEXT: 1 1 1.00 * str x1, [x10]
+# CHECK-NEXT: 1 3 1.00 * ldr x2, [x10]
+# CHECK-NEXT: 1 1 1.00 * * U nop
+# CHECK-NEXT: 1 3 1.00 * ldr x2, [x10]
+# CHECK-NEXT: 1 3 1.00 * ldr x3, [x10]
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - CortexA55UnitALU
+# CHECK-NEXT: [0.1] - CortexA55UnitALU
+# CHECK-NEXT: [1] - CortexA55UnitB
+# CHECK-NEXT: [2] - CortexA55UnitDiv
+# CHECK-NEXT: [3.0] - CortexA55UnitFPALU
+# CHECK-NEXT: [3.1] - CortexA55UnitFPALU
+# CHECK-NEXT: [4] - CortexA55UnitFPDIV
+# CHECK-NEXT: [5.0] - CortexA55UnitFPMAC
+# CHECK-NEXT: [5.1] - CortexA55UnitFPMAC
+# CHECK-NEXT: [6] - CortexA55UnitLd
+# CHECK-NEXT: [7] - CortexA55UnitMAC
+# CHECK-NEXT: [8] - CortexA55UnitSt
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8]
+# CHECK-NEXT: - - 1.00 - - - - - - 3.00 - 2.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - 1.00 str x1, [x10]
+# CHECK-NEXT: - - - - - - - - - - - 1.00 str x1, [x10]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr x2, [x10]
+# CHECK-NEXT: - - 1.00 - - - - - - - - - nop
+# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr x2, [x10]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr x3, [x10]
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012345678
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DE . . . . str x1, [x10]
+# CHECK-NEXT: [0,1] .DE . . . . str x1, [x10]
+# CHECK-NEXT: [0,2] .DeeE. . . . ldr x2, [x10]
+# CHECK-NEXT: [0,3] . DE. . . . nop
+# CHECK-NEXT: [0,4] . DeeE . . . ldr x2, [x10]
+# CHECK-NEXT: [0,5] . DeeE . . . ldr x3, [x10]
+# CHECK-NEXT: [1,0] . DE . . . str x1, [x10]
+# CHECK-NEXT: [1,1] . .DE . . . str x1, [x10]
+# CHECK-NEXT: [1,2] . .DeeE. . . ldr x2, [x10]
+# CHECK-NEXT: [1,3] . . DE. . . nop
+# CHECK-NEXT: [1,4] . . DeeE . . ldr x2, [x10]
+# CHECK-NEXT: [1,5] . . DeeE . . ldr x3, [x10]
+# CHECK-NEXT: [2,0] . . DE . . str x1, [x10]
+# CHECK-NEXT: [2,1] . . .DE . . str x1, [x10]
+# CHECK-NEXT: [2,2] . . .DeeE. . ldr x2, [x10]
+# CHECK-NEXT: [2,3] . . . DE. . nop
+# CHECK-NEXT: [2,4] . . . DeeE. ldr x2, [x10]
+# CHECK-NEXT: [2,5] . . . DeeE ldr x3, [x10]
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 3 0.0 0.0 0.0 str x1, [x10]
+# CHECK-NEXT: 1. 3 0.0 0.0 0.0 str x1, [x10]
+# CHECK-NEXT: 2. 3 0.0 0.0 0.0 ldr x2, [x10]
+# CHECK-NEXT: 3. 3 0.0 0.0 0.0 nop
+# CHECK-NEXT: 4. 3 0.0 0.0 0.0 ldr x2, [x10]
+# CHECK-NEXT: 5. 3 0.0 0.0 0.0 ldr x3, [x10]
+# CHECK-NEXT: 3 0.0 0.0 0.0 <total>