ARM: dts: imx6qdl: add multiplexer controls
authorPhilipp Zabel <p.zabel@pengutronix.de>
Mon, 12 Jun 2017 18:23:54 +0000 (11:23 -0700)
committerShawn Guo <shawnguo@kernel.org>
Wed, 14 Jun 2017 15:06:02 +0000 (23:06 +0800)
The IOMUXC General Purpose Register space contains various bitfields
that control video bus multiplexers. Describe them using a mmio-mux
node. The placement of the IPU CSI video mux controls differs between
i.MX6D/Q and i.MX6S/DL.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/imx6dl.dtsi
arch/arm/boot/dts/imx6q.dtsi
arch/arm/boot/dts/imx6qdl.dtsi

index 7aa120f..10bc9d1 100644 (file)
                      "di0", "di1";
 };
 
+&mux {
+       mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
+                       <0x34 0x00000038>, /* IPU_CSI1_MUX */
+                       <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
+                       <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
+                       <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
+                       <0x28 0x00000003>, /* DCIC1_MUX_CTL */
+                       <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
+};
+
 &vpu {
        compatible = "fsl,imx6dl-vpu", "cnm,coda960";
 };
index dd33849..1a14ae2 100644 (file)
        };
 };
 
+&mux {
+       mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
+                       <0x04 0x00100000>, /* MIPI_IPU2_MUX */
+                       <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
+                       <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
+                       <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
+                       <0x28 0x00000003>, /* DCIC1_MUX_CTL */
+                       <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
+};
+
 &vpu {
        compatible = "fsl,imx6q-vpu", "cnm,coda960";
 };
index f325411..4ea7d86 100644 (file)
                        };
 
                        gpr: iomuxc-gpr@020e0000 {
-                               compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
+                               compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
                                reg = <0x020e0000 0x38>;
+
+                               mux: mux-controller {
+                                       compatible = "mmio-mux";
+                                       #mux-control-cells = <1>;
+                               };
                        };
 
                        iomuxc: iomuxc@020e0000 {