void r600_inval_vertex_cache(struct r600_context *ctx)
{
- if (ctx->family == CHIP_RV610 ||
- ctx->family == CHIP_RV620 ||
- ctx->family == CHIP_RS780 ||
- ctx->family == CHIP_RS880 ||
- ctx->family == CHIP_RV710 ||
- ctx->family == CHIP_CEDAR ||
- ctx->family == CHIP_PALM ||
- ctx->family == CHIP_SUMO ||
- ctx->family == CHIP_SUMO2 ||
- ctx->family == CHIP_CAICOS ||
- ctx->family == CHIP_CAYMAN ||
- ctx->family == CHIP_ARUBA) {
+ if (ctx->has_vertex_cache) {
+ ctx->surface_sync_cmd.flush_flags |= S_0085F0_VC_ACTION_ENA(1);
+ } else {
/* Some GPUs don't have the vertex cache and must use the texture cache instead. */
ctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1);
- } else {
- ctx->surface_sync_cmd.flush_flags |= S_0085F0_VC_ACTION_ENA(1);
}
r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
}
if (r600_context_init(rctx))
goto fail;
rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
+ rctx->has_vertex_cache = !(rctx->family == CHIP_RV610 ||
+ rctx->family == CHIP_RV620 ||
+ rctx->family == CHIP_RS780 ||
+ rctx->family == CHIP_RS880 ||
+ rctx->family == CHIP_RV710);
break;
case EVERGREEN:
case CAYMAN:
if (evergreen_context_init(rctx))
goto fail;
rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
+ rctx->has_vertex_cache = !(rctx->family == CHIP_CEDAR ||
+ rctx->family == CHIP_PALM ||
+ rctx->family == CHIP_SUMO ||
+ rctx->family == CHIP_SUMO2 ||
+ rctx->family == CHIP_CAICOS ||
+ rctx->family == CHIP_CAYMAN ||
+ rctx->family == CHIP_ARUBA);
break;
default:
R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
struct blitter_context *blitter;
enum radeon_family family;
enum chip_class chip_class;
+ boolean has_vertex_cache;
unsigned r6xx_num_clause_temp_gprs;
void *custom_dsa_flush;
struct r600_screen *screen;