2014-07-16 Yvan Roux <yvan.roux@linaro.org>

	Backport from trunk r211408, 211416.
	2014-06-10  Marcus Shawcroft  <marcus.shawcroft@arm.com>

	* config/aarch64/aarch64.c (aarch64_save_or_restore_fprs): Fix
	REG_CFA_RESTORE mode.

	2014-06-10  Jiong Wang  <jiong.wang@arm.com>

	* config/aarch64/aarch64.c (aarch64_save_or_restore_fprs)
	(aarch64_save_or_restore_callee_save_registers): Fix layout.

git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212689 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog.linaro b/gcc/ChangeLog.linaro
index 56810ea..4fcdfad 100644 (file)
--- a/gcc/ChangeLog.linaro
+++ b/gcc/ChangeLog.linaro
@@ -1,5 +1,18 @@
 2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
 
+       Backport from trunk r211408, 211416.
+       2014-06-10  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+       * config/aarch64/aarch64.c (aarch64_save_or_restore_fprs): Fix
+       REG_CFA_RESTORE mode.
+
+       2014-06-10  Jiong Wang  <jiong.wang@arm.com>
+
+       * config/aarch64/aarch64.c (aarch64_save_or_restore_fprs)
+       (aarch64_save_or_restore_callee_save_registers): Fix layout.
+
+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
+
        Backport from trunk r211418.
        2014-06-10  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index fd9fb6f..e9bf85e 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1921,7 +1921,6 @@ aarch64_save_or_restore_fprs (int start_offset, int increment,
   rtx (*gen_mem_ref)(enum machine_mode, rtx)
     = (frame_pointer_needed)? gen_frame_mem : gen_rtx_MEM;
 
-
   for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++)
     {
       if (aarch64_register_saved_on_entry (regno))
@@ -1939,10 +1938,12 @@ aarch64_save_or_restore_fprs (int start_offset, int increment,
            {
              /* Empty loop.  */
            }
+
          if (regno2 <= V31_REGNUM &&
              aarch64_register_saved_on_entry (regno2))
            {
              rtx mem2;
+
              /* Next highest register to be saved.  */
              mem2 = gen_mem_ref (DFmode,
                                  plus_constant
@@ -1968,10 +1969,10 @@ aarch64_save_or_restore_fprs (int start_offset, int increment,
                                gen_rtx_REG (DFmode, regno2));
                }
 
-                 /* The first part of a frame-related parallel insn
-                    is always assumed to be relevant to the frame
-                    calculations; subsequent parts, are only
-                    frame-related if explicitly marked.  */
+             /* The first part of a frame-related parallel insn is
+                always assumed to be relevant to the frame
+                calculations; subsequent parts, are only
+                frame-related if explicitly marked.  */
              RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
              regno = regno2;
              start_offset += increment * 2;
@@ -1984,14 +1985,13 @@ aarch64_save_or_restore_fprs (int start_offset, int increment,
                {
                  insn = emit_move_insn (gen_rtx_REG (DFmode, regno), mem);
                  add_reg_note (insn, REG_CFA_RESTORE,
-                               gen_rtx_REG (DImode, regno));
+                               gen_rtx_REG (DFmode, regno));
                }
              start_offset += increment;
            }
          RTX_FRAME_RELATED_P (insn) = 1;
        }
     }
-
 }
 
 
@@ -1999,7 +1999,7 @@ aarch64_save_or_restore_fprs (int start_offset, int increment,
    restore's have to happen.  */
 static void
 aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT offset,
-                                           bool restore)
+                                              bool restore)
 {
   rtx insn;
   rtx base_rtx = stack_pointer_rtx;
@@ -2031,6 +2031,7 @@ aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT offset,
              aarch64_register_saved_on_entry (regno2))
            {
              rtx mem2;
+
              /* Next highest register to be saved.  */
              mem2 = gen_mem_ref (Pmode,
                                  plus_constant
@@ -2054,12 +2055,11 @@ aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT offset,
                  add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, regno2));
                }
 
-                 /* The first part of a frame-related parallel insn
-                    is always assumed to be relevant to the frame
-                    calculations; subsequent parts, are only
-                    frame-related if explicitly marked.  */
-             RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0,
-                                           1)) = 1;
+             /* The first part of a frame-related parallel insn is
+                always assumed to be relevant to the frame
+                calculations; subsequent parts, are only
+                frame-related if explicitly marked.  */
+             RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
              regno = regno2;
              start_offset += increment * 2;
            }
@@ -2079,7 +2079,6 @@ aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT offset,
     }
 
   aarch64_save_or_restore_fprs (start_offset, increment, restore, base_rtx);
-
 }
 
 /* AArch64 stack frames generated by this compiler look like: