[RISCV] Add vfabs.v pseudo instruction.
authorHsiangkai Wang <kai.wang@sifive.com>
Sat, 27 Mar 2021 11:40:09 +0000 (19:40 +0800)
committerHsiangkai Wang <kai.wang@sifive.com>
Sun, 28 Mar 2021 02:24:05 +0000 (10:24 +0800)
Differential Revision: https://reviews.llvm.org/D99454

llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/test/MC/RISCV/rvv/aliases.s

index 6f71a8e..5f51aac 100644 (file)
@@ -818,6 +818,8 @@ defm VFSGNJX_V : VALU_FV_V_F<"vfsgnjx", 0b001010>;
 
 def : InstAlias<"vfneg.v $vd, $vs$vm",
                 (VFSGNJN_VV VR:$vd, VR:$vs, VR:$vs, VMaskOp:$vm)>;
+def : InstAlias<"vfabs.v $vd, $vs$vm",
+                (VFSGNJX_VV VR:$vd, VR:$vs, VR:$vs, VMaskOp:$vm)>;
 
 // Vector Floating-Point Compare Instructions
 let RVVConstraint = NoConstraint in {
index ebe9e79..ba41594 100644 (file)
@@ -75,3 +75,6 @@ vncvt.x.x.w v2, v1, v0.t
 # ALIAS:    vfneg.v         v2, v1, v0.t     # encoding: [0x57,0x91,0x10,0x24]
 # NO-ALIAS: vfsgnjn.vv      v2, v1, v1, v0.t # encoding: [0x57,0x91,0x10,0x24]
 vfneg.v v2, v1, v0.t 
+# ALIAS:    vfabs.v         v2, v1, v0.t     # encoding: [0x57,0x91,0x10,0x28]
+# NO-ALIAS: vfsgnjx.vv      v2, v1, v1, v0.t # encoding: [0x57,0x91,0x10,0x28]
+vfabs.v v2, v1, v0.t