#define ET_MSI_TC 0x00070000
/*
- * structure for Loopback reg in global address map
- * located at address 0x0034
+ * Loopback reg located at address 0x0034
*/
-typedef union _LOOPBACK_t {
- u32 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u32 unused:30; /* bits 2-31 */
- u32 dma_loopback:1; /* bit 1 */
- u32 mac_loopback:1; /* bit 0 */
-#else
- u32 mac_loopback:1; /* bit 0 */
- u32 dma_loopback:1; /* bit 1 */
- u32 unused:30; /* bits 2-31 */
-#endif
- } bits;
-} LOOPBACK_t, *PLOOPBACK_t;
+
+#define ET_LOOP_MAC 0x00000001
+#define ET_LOOP_DMA 0x00000002
/*
* GLOBAL Module of JAGCore Address Mapping
u32 sw_reset; /* 0x0028 */
u32 slv_timer; /* 0x002C */
u32 msi_config; /* 0x0030 */
- LOOPBACK_t loopback; /* 0x0034 */
+ u32 loopback; /* 0x0034 */
u32 watchdog_timer; /* 0x0038 */
} GLOBAL_t, *PGLOBAL_t;
}
/* Initialize the loopback register. Disable all loopbacks. */
- writel(0, ®s->loopback.value);
+ writel(0, ®s->loopback);
} else {
/* For PHY Line loopback, the memory is configured as if Tx
* and Rx both have all the memory. This is because the
writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr);
/* Initialize the loopback register (MAC loopback). */
- writel(1, ®s->loopback);
+ writel(ET_LOOP_MAC, ®s->loopback);
}
/* MSI Register */