[X86] Add TDX instructions.

For more details about these instructions, please refer to the latest TDX document: https://software.intel.com/content/www/us/en/develop/articles/intel-trust-domain-extensions.html

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D88006

diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index 14ca9f8..99a9ce2 100644 (file)
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -3092,6 +3092,8 @@ include "X86InstrSVM.td"
 include "X86InstrTSX.td"
 include "X86InstrSGX.td"
 
+include "X86InstrTDX.td"
+
 // AMX instructions
 include "X86InstrAMX.td"
 

diff --git a/llvm/lib/Target/X86/X86InstrTDX.td b/llvm/lib/Target/X86/X86InstrTDX.td
new file mode 100644 (file)
index 0000000..8d7cd60
--- /dev/null
+++ b/llvm/lib/Target/X86/X86InstrTDX.td
@@ -0,0 +1,39 @@
+//===- X86InstrTDX.td - TDX Instruction Set Extension -*- tablegen -*===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the instructions that make up the Intel TDX instruction
+// set.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// TDX instructions
+
+// 64-bit only instructions
+let SchedRW = [WriteSystem], Predicates = [In64BitMode] in {
+// SEAMCALL - Call to SEAM VMX-root Operation Module
+def SEAMCALL : I<0x01, MRM_CF, (outs), (ins),
+             "seamcall", []>, PD;
+
+// SEAMRET - Return to Legacy VMX-root Operation
+def SEAMRET : I<0x01, MRM_CD, (outs), (ins),
+             "seamret", []>, PD;
+
+// SEAMOPS - SEAM Operations
+def SEAMOPS : I<0x01, MRM_CE, (outs), (ins),
+             "seamops", []>, PD;
+
+} // SchedRW
+
+// common instructions
+let SchedRW = [WriteSystem] in {
+// TDCALL - Call SEAM Module Functions
+def TDCALL : I<0x01, MRM_CC, (outs), (ins),
+             "tdcall", []>, PD;
+
+} // SchedRW

diff --git a/llvm/test/MC/Disassembler/X86/x86-32.txt b/llvm/test/MC/Disassembler/X86/x86-32.txt
index baa12bf..d223a72 100644 (file)
--- a/llvm/test/MC/Disassembler/X86/x86-32.txt
+++ b/llvm/test/MC/Disassembler/X86/x86-32.txt
@@ -997,3 +997,6 @@
 
 # CHECK: xresldtrk
 0xf2 0x0f 0x01 0xe9
+
+#CHECK: tdcall
+0x66 0x0f 0x01 0xcc

diff --git a/llvm/test/MC/Disassembler/X86/x86-64.txt b/llvm/test/MC/Disassembler/X86/x86-64.txt
index 2237484..d02cf4c 100644 (file)
--- a/llvm/test/MC/Disassembler/X86/x86-64.txt
+++ b/llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -700,3 +700,15 @@
 
 # CHECK: xresldtrk
 0xf2 0x0f 0x01 0xe9
+
+#CHECK: seamcall
+0x66 0x0f 0x01 0xcf
+
+#CHECK: seamret
+0x66 0x0f 0x01 0xcd
+
+#CHECK: seamops
+0x66 0x0f 0x01 0xce
+
+#CHECK: tdcall
+0x66 0x0f 0x01 0xcc

diff --git a/llvm/test/MC/X86/x86-32-coverage.s b/llvm/test/MC/X86/x86-32-coverage.s
index 4e199c7..906d594 100644 (file)
--- a/llvm/test/MC/X86/x86-32-coverage.s
+++ b/llvm/test/MC/X86/x86-32-coverage.s
@@ -10888,3 +10888,7 @@ xsusldtrk
 // CHECK: xresldtrk
 // CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
 xresldtrk
+
+// CHECK: tdcall
+// CHECK: encoding: [0x66,0x0f,0x01,0xcc]
+tdcall
\ No newline at end of file

diff --git a/llvm/test/MC/X86/x86-64.s b/llvm/test/MC/X86/x86-64.s
index 911aa29..eb4ac1d 100644 (file)
--- a/llvm/test/MC/X86/x86-64.s
+++ b/llvm/test/MC/X86/x86-64.s
@@ -1998,3 +1998,19 @@ movl $1, (%rbp,%rbx,4)
 movl $1, (%r13,%rbx,4)
 {disp8} movl $1, (%r13,%rbx,4)
 {disp32} movl $1, (%r13,%rbx,4)
+
+// CHECK: seamcall
+// CHECK: encoding: [0x66,0x0f,0x01,0xcf]
+seamcall
+
+// CHECK: seamret
+// CHECK: encoding: [0x66,0x0f,0x01,0xcd]
+seamret
+
+// CHECK: seamops
+// CHECK: encoding: [0x66,0x0f,0x01,0xce]
+seamops
+
+// CHECK: tdcall
+// CHECK: encoding: [0x66,0x0f,0x01,0xcc]
+tdcall