habanalabs: update goya firmware register map
authorOded Gabbay <oded.gabbay@gmail.com>
Thu, 5 Mar 2020 13:12:20 +0000 (15:12 +0200)
committerOded Gabbay <oded.gabbay@gmail.com>
Tue, 24 Mar 2020 08:54:17 +0000 (10:54 +0200)
Use specific values in enum of register map to be able to deprecate old
values.

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
drivers/misc/habanalabs/include/goya/goya_reg_map.h
drivers/misc/habanalabs/include/hl_boot_if.h

index cd89723..0806128 100644 (file)
 /*
  * PSOC scratch-pad registers
  */
-#define mmCPU_PQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_0
-#define mmCPU_PQ_BASE_ADDR_HIGH        mmPSOC_GLOBAL_CONF_SCRATCHPAD_1
-#define mmCPU_EQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_2
-#define mmCPU_EQ_BASE_ADDR_HIGH        mmPSOC_GLOBAL_CONF_SCRATCHPAD_3
-#define mmCPU_EQ_LENGTH                mmPSOC_GLOBAL_CONF_SCRATCHPAD_4
-#define mmCPU_PQ_LENGTH                mmPSOC_GLOBAL_CONF_SCRATCHPAD_5
-#define mmCPU_EQ_CI            mmPSOC_GLOBAL_CONF_SCRATCHPAD_6
-#define mmCPU_PQ_INIT_STATUS   mmPSOC_GLOBAL_CONF_SCRATCHPAD_7
-#define mmCPU_CQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_8
-#define mmCPU_CQ_BASE_ADDR_HIGH        mmPSOC_GLOBAL_CONF_SCRATCHPAD_9
-#define mmCPU_CQ_LENGTH                mmPSOC_GLOBAL_CONF_SCRATCHPAD_10
-#define mmUPD_STS              mmPSOC_GLOBAL_CONF_SCRATCHPAD_26
-#define mmUPD_CMD              mmPSOC_GLOBAL_CONF_SCRATCHPAD_27
-#define mmPREBOOT_VER_OFFSET   mmPSOC_GLOBAL_CONF_SCRATCHPAD_28
-#define mmUBOOT_VER_OFFSET     mmPSOC_GLOBAL_CONF_SCRATCHPAD_29
-#define mmUBOOT_OFFSET         mmPSOC_GLOBAL_CONF_SCRATCHPAD_30
-#define mmBTL_ID               mmPSOC_GLOBAL_CONF_SCRATCHPAD_31
+#define mmCPU_PQ_BASE_ADDR_LOW                 mmPSOC_GLOBAL_CONF_SCRATCHPAD_0
+#define mmCPU_PQ_BASE_ADDR_HIGH                        mmPSOC_GLOBAL_CONF_SCRATCHPAD_1
+#define mmCPU_EQ_BASE_ADDR_LOW                 mmPSOC_GLOBAL_CONF_SCRATCHPAD_2
+#define mmCPU_EQ_BASE_ADDR_HIGH                        mmPSOC_GLOBAL_CONF_SCRATCHPAD_3
+#define mmCPU_EQ_LENGTH                                mmPSOC_GLOBAL_CONF_SCRATCHPAD_4
+#define mmCPU_PQ_LENGTH                                mmPSOC_GLOBAL_CONF_SCRATCHPAD_5
+#define mmCPU_EQ_CI                            mmPSOC_GLOBAL_CONF_SCRATCHPAD_6
+#define mmCPU_PQ_INIT_STATUS                   mmPSOC_GLOBAL_CONF_SCRATCHPAD_7
+#define mmCPU_CQ_BASE_ADDR_LOW                 mmPSOC_GLOBAL_CONF_SCRATCHPAD_8
+#define mmCPU_CQ_BASE_ADDR_HIGH                        mmPSOC_GLOBAL_CONF_SCRATCHPAD_9
+#define mmCPU_CQ_LENGTH                                mmPSOC_GLOBAL_CONF_SCRATCHPAD_10
+#define mmCPU_BOOT_ERR0                                mmPSOC_GLOBAL_CONF_SCRATCHPAD_24
+#define mmCPU_BOOT_ERR1                                mmPSOC_GLOBAL_CONF_SCRATCHPAD_25
+#define mmUPD_STS                              mmPSOC_GLOBAL_CONF_SCRATCHPAD_26
+#define mmUPD_CMD                              mmPSOC_GLOBAL_CONF_SCRATCHPAD_27
+#define mmPREBOOT_VER_OFFSET                   mmPSOC_GLOBAL_CONF_SCRATCHPAD_28
+#define mmUBOOT_VER_OFFSET                     mmPSOC_GLOBAL_CONF_SCRATCHPAD_29
+#define mmRDWR_TEST                            mmPSOC_GLOBAL_CONF_SCRATCHPAD_30
+#define mmBTL_ID                               mmPSOC_GLOBAL_CONF_SCRATCHPAD_31
 
-#define mmHW_STATE             mmPSOC_GLOBAL_CONF_APP_STATUS
+#define mmHW_STATE                             mmPSOC_GLOBAL_CONF_APP_STATUS
+#define mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS     mmPSOC_GLOBAL_CONF_WARM_REBOOT
 
 #endif /* GOYA_REG_MAP_H_ */
index 2853a2d..f7992a6 100644 (file)
@@ -8,20 +8,35 @@
 #ifndef HL_BOOT_IF_H
 #define HL_BOOT_IF_H
 
+#define LKD_HARD_RESET_MAGIC           0xED7BD694
+
+/* CPU error bits in BOOT_ERROR registers */
+#define CPU_BOOT_ERR0_DRAM_INIT_FAIL           (1 << 0)
+#define CPU_BOOT_ERR0_FIT_CORRUPTED            (1 << 1)
+#define CPU_BOOT_ERR0_TS_INIT_FAIL             (1 << 2)
+#define CPU_BOOT_ERR0_DRAM_SKIPPED             (1 << 3)
+#define CPU_BOOT_ERR0_BMC_WAIT_SKIPPED         (1 << 4)
+#define CPU_BOOT_ERR0_NIC_DATA_NOT_RDY         (1 << 5)
+#define CPU_BOOT_ERR0_NIC_FW_FAIL              (1 << 6)
+#define CPU_BOOT_ERR0_ENABLED                  (1 << 31)
+
 enum cpu_boot_status {
        CPU_BOOT_STATUS_NA = 0,         /* Default value after reset of chip */
-       CPU_BOOT_STATUS_IN_WFE,
-       CPU_BOOT_STATUS_DRAM_RDY,
-       CPU_BOOT_STATUS_SRAM_AVAIL,
-       CPU_BOOT_STATUS_IN_BTL,         /* BTL is H/W FSM */
-       CPU_BOOT_STATUS_IN_PREBOOT,
-       CPU_BOOT_STATUS_IN_SPL,
-       CPU_BOOT_STATUS_IN_UBOOT,
-       CPU_BOOT_STATUS_DRAM_INIT_FAIL,
-       CPU_BOOT_STATUS_FIT_CORRUPTED,
-       CPU_BOOT_STATUS_UBOOT_NOT_READY,
-       CPU_BOOT_STATUS_RESERVED,
-       CPU_BOOT_STATUS_TS_INIT_FAIL,
+       CPU_BOOT_STATUS_IN_WFE = 1,
+       CPU_BOOT_STATUS_DRAM_RDY = 2,
+       CPU_BOOT_STATUS_SRAM_AVAIL = 3,
+       CPU_BOOT_STATUS_IN_BTL = 4,     /* BTL is H/W FSM */
+       CPU_BOOT_STATUS_IN_PREBOOT = 5,
+       CPU_BOOT_STATUS_IN_SPL = 6,
+       CPU_BOOT_STATUS_IN_UBOOT = 7,
+       CPU_BOOT_STATUS_DRAM_INIT_FAIL, /* deprecated - will be removed */
+       CPU_BOOT_STATUS_FIT_CORRUPTED,  /* deprecated - will be removed */
+       CPU_BOOT_STATUS_UBOOT_NOT_READY = 10,
+       CPU_BOOT_STATUS_NIC_FW_RDY = 11,
+       CPU_BOOT_STATUS_TS_INIT_FAIL,   /* deprecated - will be removed */
+       CPU_BOOT_STATUS_DRAM_SKIPPED,   /* deprecated - will be removed */
+       CPU_BOOT_STATUS_BMC_WAITING_SKIPPED, /* deprecated - will be removed */
+       CPU_BOOT_STATUS_READY_TO_BOOT = 15,
 };
 
 enum kmd_msg {