drm/msm/dpu: Fix slice_last_group_size calculation

[ Upstream commit c223059e6f8340f7eac2319470984cbfc39c433b ]

Correct the math for slice_last_group_size so that it matches the
calculations downstream.

Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/539269/
Link: https://lore.kernel.org/r/20230329-rfc-msm-dsc-helper-v14-7-bafc7be95691@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
index 3662df6..c8f1455 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
@@ -52,9 +52,10 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
        if (is_cmd_mode)
                initial_lines += 1;
 
-       slice_last_group_size = 3 - (dsc->slice_width % 3);
+       slice_last_group_size = (dsc->slice_width + 2) % 3;
+
        data = (initial_lines << 20);
-       data |= ((slice_last_group_size - 1) << 18);
+       data |= (slice_last_group_size << 18);
        /* bpp is 6.4 format, 4 LSBs bits are for fractional part */
        data |= (dsc->bits_per_pixel << 8);
        data |= (dsc->block_pred_enable << 7);