sunxi: Use PG3 - PG8 as io-pins for mmc1

None of the known sunxi devices actually use mmc1 routed through PH, where
as some devices do actually use mmc1 routed through PG, so change the routing
of mmc1 to PG. If in the future we encounter devices with mmc1 routed through
PH, we will need to change things to be a bit more flexible.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index ba7e69b..59122db 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -117,6 +117,8 @@ enum sunxi_gpio_number {
 #define SUN5I_GPB19_UART0_TX   2
 #define SUN5I_GPB20_UART0_RX   2
 
+#define SUN5I_GPG3_SDC1                2
+
 #define SUN5I_GPG3_UART1_TX    4
 #define SUN5I_GPG4_UART1_RX    4
 

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index f310e8d..03890c8 100644 (file)
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -71,9 +71,9 @@ static void mmc_pinmux_setup(int sdc)
                break;
 
        case 1:
-               /* CMD-PH22, CLK-PH23, D0~D3-PH24~27 : 5 */
-               for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
-                       sunxi_gpio_set_cfgpin(pin, SUN4I_GPH22_SDC1);
+               /* CMD-PG3, CLK-PG4, D0~D3-PG5-8 */
+               for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
+                       sunxi_gpio_set_cfgpin(pin, SUN5I_GPG3_SDC1);
                        sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
                        sunxi_gpio_set_drv(pin, 2);
                }