drm/amd/display: Remove FPU guards from the DML folder

As part of the programming expectation for using DML functions, DC
requires that any DML function invoked outside DML uses:

 DC_FP_START();
 ... dml function ...
 DC_FP_END();

Additionally, all the DML functions that can be invoked outside the DML
folder call the function dc_assert_fp_enabled(), which is responsible
for triggering a warning in the case that the DML function was not
guarded by the DC_FP_START/END. For this reason, call DC_FP_START/END
inside DML is wrong, and this commit removes all of those references.

Tested-by: Mark Broadworth <mark.broadworth@amd.com>
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
index e1e92da..d4c0f9c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
@@ -520,9 +520,7 @@ void dcn30_fpu_calculate_wm_and_dlg(
                pipe_idx++;
        }
 
-       DC_FP_START();
        dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
-       DC_FP_END();
 
        if (!pstate_en)
                /* Restore full p-state latency */

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 819de0f..d8e68f1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1191,9 +1191,7 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,
                        }
                } else {
                        // Most populate phantom DLG params before programming hardware / timing for phantom pipe
-                       DC_FP_START();
                        dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt);
-                       DC_FP_END();
 
                        /* Call validate_apply_pipe_split flags after calling DML getters for
                         * phantom dlg params, or some of the VBA params indicating pipe split
@@ -1494,11 +1492,8 @@ bool dcn32_internal_validate_bw(struct dc *dc,
 
        dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
 
-       if (!fast_validate) {
-               DC_FP_START();
+       if (!fast_validate)
                dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt);
-               DC_FP_END();
-       }
 
        if (fast_validate ||
                        (dc->debug.dml_disallow_alternate_prefetch_modes &&
@@ -2145,9 +2140,7 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
                entry.fabricclk_mhz = 0;
                entry.dram_speed_mts = 0;
 
-               DC_FP_START();
                insert_entry_into_table_sorted(table, num_entries, &entry);
-               DC_FP_END();
        }
 
        // Insert the max DCFCLK
@@ -2155,9 +2148,7 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
        entry.fabricclk_mhz = 0;
        entry.dram_speed_mts = 0;
 
-       DC_FP_START();
        insert_entry_into_table_sorted(table, num_entries, &entry);
-       DC_FP_END();
 
        // Insert the UCLK DPMS
        for (i = 0; i < num_uclk_dpms; i++) {
@@ -2165,9 +2156,7 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
                entry.fabricclk_mhz = 0;
                entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;
 
-               DC_FP_START();
                insert_entry_into_table_sorted(table, num_entries, &entry);
-               DC_FP_END();
        }
 
        // If FCLK is coarse grained, insert individual DPMs.
@@ -2177,9 +2166,7 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
                        entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
                        entry.dram_speed_mts = 0;
 
-                       DC_FP_START();
                        insert_entry_into_table_sorted(table, num_entries, &entry);
-                       DC_FP_END();
                }
        }
        // If FCLK fine grained, only insert max
@@ -2188,9 +2175,7 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
                entry.fabricclk_mhz = max_fclk_mhz;
                entry.dram_speed_mts = 0;
 
-               DC_FP_START();
                insert_entry_into_table_sorted(table, num_entries, &entry);
-               DC_FP_END();
        }
 
        // At this point, the table contains all "points of interest" based on