+2007-08-30 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/amd.s: Add rdtscp.
+ * gas/i386/amd.d: Updated.
+
+ * gas/i386/mem-intel.d: Update invlpg for BYTE PTR.
+ * gas/i386/x86-64-mem-intel.d: Likewise.
+
+ * gas/i386/x86-64-opcode.s: Add swapgs.
+ * gas/i386/x86-64-opcode.d: Updated.
+
2007-08-29 Daniel Jacobowitz <dan@codesourcery.com>
* gas/lns/lns-duplicate.d, gas/lns/lns-duplicate.s: New.
Disassembly of section .text:
-0+000 <foo>:
- 0: 0f 0d 03 [ ]*prefetch \(%ebx\)
- 3: 0f 0d 0c 75 00 10 00 00 [ ]*prefetchw 0x1000\(,%esi,2\)
- b: 0f 0e [ ]*femms
- d: 0f 0f 00 bf [ ]*pavgusb \(%eax\),%mm0
- 11: 0f 0f 48 02 1d [ ]*pf2id 0x2\(%eax\),%mm1
- 16: 0f 0f 90 00 01 00 00 ae [ ]*pfacc 0x100\(%eax\),%mm2
- 1e: 0f 0f 1e 9e [ ]*pfadd \(%esi\),%mm3
- 22: 0f 0f 66 02 b0 [ ]*pfcmpeq 0x2\(%esi\),%mm4
- 27: 0f 0f ae 90 90 00 00 90 [ ]*pfcmpge 0x9090\(%esi\),%mm5
- 2f: 0f 0f 74 75 00 a0 [ ]*pfcmpgt 0x0\(%ebp,%esi,2\),%mm6
- 35: 0f 0f 7c 75 02 a4 [ ]*pfmax 0x2\(%ebp,%esi,2\),%mm7
- 3b: 0f 0f 84 75 90 90 90 90 94 [ ]*pfmin -0x6f6f6f70\(%ebp,%esi,2\),%mm0
- 44: 0f 0f 0d 04 00 00 00 b4 [ ]*pfmul 0x4,%mm1
- 4c: 2e 0f 0f 54 c3 07 96 [ ]*pfrcp %cs:0x7\(%ebx,%eax,8\),%mm2
- 53: 0f 0f d8 a6 [ ]*pfrcpit1 %mm0,%mm3
- 57: 0f 0f e1 b6 [ ]*pfrcpit2 %mm1,%mm4
- 5b: 0f 0f ea a7 [ ]*pfrsqit1 %mm2,%mm5
- 5f: 0f 0f f3 97 [ ]*pfrsqrt %mm3,%mm6
- 63: 0f 0f fc 9a [ ]*pfsub %mm4,%mm7
- 67: 0f 0f c5 aa [ ]*pfsubr %mm5,%mm0
- 6b: 0f 0f ce 0d [ ]*pi2fd %mm6,%mm1
- 6f: 0f 0f d7 b7 [ ]*pmulhrw %mm7,%mm2
- 73: 2e 0f [ ]*\(bad\)
- 75: 0f 54 c3 [ ]*andps %xmm3,%xmm0
- 78: 07 [ ]*pop %es
- 79: c3 [ ]*ret
- 7a: 90 [ ]*nop
- 7b: 90 [ ]*nop
- 7c: 90 [ ]*nop
- 7d: 90 [ ]*nop
- 7e: 90 [ ]*nop
- 7f: 90 [ ]*nop
+0+ <foo>:
+[ ]*[a-f0-9]+: 0f 0d 03 prefetch \(%ebx\)
+[ ]*[a-f0-9]+: 0f 0d 0c 75 00 10 00 00 prefetchw 0x1000\(,%esi,2\)
+[ ]*[a-f0-9]+: 0f 0e femms
+[ ]*[a-f0-9]+: 0f 0f 00 bf pavgusb \(%eax\),%mm0
+[ ]*[a-f0-9]+: 0f 0f 48 02 1d pf2id 0x2\(%eax\),%mm1
+[ ]*[a-f0-9]+: 0f 0f 90 00 01 00 00 ae pfacc 0x100\(%eax\),%mm2
+[ ]*[a-f0-9]+: 0f 0f 1e 9e pfadd \(%esi\),%mm3
+[ ]*[a-f0-9]+: 0f 0f 66 02 b0 pfcmpeq 0x2\(%esi\),%mm4
+[ ]*[a-f0-9]+: 0f 0f ae 90 90 00 00 90 pfcmpge 0x9090\(%esi\),%mm5
+[ ]*[a-f0-9]+: 0f 0f 74 75 00 a0 pfcmpgt 0x0\(%ebp,%esi,2\),%mm6
+[ ]*[a-f0-9]+: 0f 0f 7c 75 02 a4 pfmax 0x2\(%ebp,%esi,2\),%mm7
+[ ]*[a-f0-9]+: 0f 0f 84 75 90 90 90 90 94 pfmin -0x6f6f6f70\(%ebp,%esi,2\),%mm0
+[ ]*[a-f0-9]+: 0f 0f 0d 04 00 00 00 b4 pfmul 0x4,%mm1
+[ ]*[a-f0-9]+: 2e 0f 0f 54 c3 07 96 pfrcp %cs:0x7\(%ebx,%eax,8\),%mm2
+[ ]*[a-f0-9]+: 0f 0f d8 a6 pfrcpit1 %mm0,%mm3
+[ ]*[a-f0-9]+: 0f 0f e1 b6 pfrcpit2 %mm1,%mm4
+[ ]*[a-f0-9]+: 0f 0f ea a7 pfrsqit1 %mm2,%mm5
+[ ]*[a-f0-9]+: 0f 0f f3 97 pfrsqrt %mm3,%mm6
+[ ]*[a-f0-9]+: 0f 0f fc 9a pfsub %mm4,%mm7
+[ ]*[a-f0-9]+: 0f 0f c5 aa pfsubr %mm5,%mm0
+[ ]*[a-f0-9]+: 0f 0f ce 0d pi2fd %mm6,%mm1
+[ ]*[a-f0-9]+: 0f 0f d7 b7 pmulhrw %mm7,%mm2
+[ ]*[a-f0-9]+: 0f 01 f9 rdtscp
+[ ]*[a-f0-9]+: 2e 0f \(bad\)
+[ ]*[a-f0-9]+: 0f 54 c3 andps %xmm3,%xmm0
+[ ]*[a-f0-9]+: 07 pop %es
+[ ]*[a-f0-9]+: c3 ret
+[ ]*[a-f0-9]+: 90 nop
+[ ]*[a-f0-9]+: 90 nop
+[ ]*[a-f0-9]+: 90 nop
+[ ]*[a-f0-9]+: 90 nop
+[ ]*[a-f0-9]+: 90 nop
+[ ]*[a-f0-9]+: 90 nop
+#pass
pi2fd %mm6,%mm1
pmulhrw %mm7,%mm2
+ rdtscp
+
# This is a 3DNow! instruction, with a prefix, that isn't quite right
# Everything's good bar the opcode suffix
.byte 0x2e, 0x0f, 0x0f, 0x54, 0xc3, 0x07, 0xc3
[ ]*[a-f0-9]+: 0f 01 0e sidtd \[esi\]
[ ]*[a-f0-9]+: 0f 01 16 lgdtd \[esi\]
[ ]*[a-f0-9]+: 0f 01 1e lidtd \[esi\]
-[ ]*[a-f0-9]+: 0f 01 3e invlpg \[esi\]
+[ ]*[a-f0-9]+: 0f 01 3e invlpg BYTE PTR \[esi\]
[ ]*[a-f0-9]+: 0f c7 0e cmpxchg8b QWORD PTR \[esi\]
[ ]*[a-f0-9]+: 0f c7 36 vmptrld QWORD PTR \[esi\]
[ ]*[a-f0-9]+: 66 0f c7 36 vmclear QWORD PTR \[esi\]
[ ]*[a-f0-9]+: 0f 01 0e sidtd \[esi\]
[ ]*[a-f0-9]+: 0f 01 16 lgdtd \[esi\]
[ ]*[a-f0-9]+: 0f 01 1e lidtd \[esi\]
-[ ]*[a-f0-9]+: 0f 01 3e invlpg \[esi\]
+[ ]*[a-f0-9]+: 0f 01 3e invlpg BYTE PTR \[esi\]
[ ]*[a-f0-9]+: 0f c7 0e cmpxchg8b QWORD PTR \[esi\]
[ ]*[a-f0-9]+: 0f c7 36 vmptrld QWORD PTR \[esi\]
[ ]*[a-f0-9]+: 66 0f c7 36 vmclear QWORD PTR \[esi\]
[ ]*[a-f0-9]+: 0f 01 0e sidt \[rsi\]
[ ]*[a-f0-9]+: 0f 01 16 lgdt \[rsi\]
[ ]*[a-f0-9]+: 0f 01 1e lidt \[rsi\]
-[ ]*[a-f0-9]+: 0f 01 3e invlpg \[rsi\]
+[ ]*[a-f0-9]+: 0f 01 3e invlpg BYTE PTR \[rsi\]
[ ]*[a-f0-9]+: 0f c7 0e cmpxchg8b QWORD PTR \[rsi\]
[ ]*[a-f0-9]+: 48 0f c7 0e cmpxchg16b OWORD PTR \[rsi\]
[ ]*[a-f0-9]+: 0f c7 36 vmptrld QWORD PTR \[rsi\]
[ ]*[a-f0-9]+: 0f 01 0e sidt \[rsi\]
[ ]*[a-f0-9]+: 0f 01 16 lgdt \[rsi\]
[ ]*[a-f0-9]+: 0f 01 1e lidt \[rsi\]
-[ ]*[a-f0-9]+: 0f 01 3e invlpg \[rsi\]
+[ ]*[a-f0-9]+: 0f 01 3e invlpg BYTE PTR \[rsi\]
[ ]*[a-f0-9]+: 0f c7 0e cmpxchg8b QWORD PTR \[rsi\]
[ ]*[a-f0-9]+: 48 0f c7 0e cmpxchg16b OWORD PTR \[rsi\]
[ ]*[a-f0-9]+: 0f c7 36 vmptrld QWORD PTR \[rsi\]
[ ]*[0-9a-f]+:[ ]+0f 00 c8[ ]+str[ ]+%eax[ ]*(#.*)*
[ ]*[0-9a-f]+:[ ]+66 0f 00 c8[ ]+str[ ]+%ax[ ]*(#.*)*
[ ]*[0-9a-f]+:[ ]+0f 00 08[ ]+str[ ]+\(%rax\)[ ]*(#.*)*
+[ ]*[a-f0-9]+: 0f 01 f8 swapgs
#pass
str %ax # 66 -- -- -- 0F 00 c8
str (%rax) # -- -- -- -- 0F 00 08
+ swapgs # -- -- -- -- 0F 01 f8
+
.p2align 4,0
+2007-08-30 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (INVLPG_Fixup): Removed.
+ (OPC_EXT_38): New.
+ (OPC_EXT_RM_5): Likewise.
+ (grps): Use OPC_EXT_38.
+ (opc_ext_table): Add OPC_EXT_38.
+ (opc_ext_rm_table): Add OPC_EXT_RM_5.
+
2007-08-29 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (SIMD_Fixup): Removed.
static void OP_3DNowSuffix (int, int);
static void OP_SIMD_Suffix (int, int);
static void SVME_Fixup (int, int);
-static void INVLPG_Fixup (int, int);
static void BadOp (void);
static void REP_Fixup (int, int);
static void CMPXCHG8B_Fixup (int, int);
#define OPC_EXT_35 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 35 } }
#define OPC_EXT_36 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 36 } }
#define OPC_EXT_37 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 37 } }
+#define OPC_EXT_38 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 38 } }
#define OPC_EXT_RM_0 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 0 } }
#define OPC_EXT_RM_1 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 1 } }
#define OPC_EXT_RM_2 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 2 } }
#define OPC_EXT_RM_3 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 3 } }
#define OPC_EXT_RM_4 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 4 } }
+#define OPC_EXT_RM_5 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 5 } }
typedef void (*op_rtn) (int bytemode, int sizeflag);
{ "smswD", { Sv } },
{ "(bad)", { XX } },
{ "lmsw", { Ew } },
- { "invlpg", { { INVLPG_Fixup, 0 } } },
+ { OPC_EXT_38 },
},
/* GRP8 */
{
{ "movhpX", { XM, EXq } },
{ "movlhpX", { XM, EXq } },
},
+ {
+ /* OPC_EXT_38 */
+ { "invlpg", { Mb } },
+ { OPC_EXT_RM_5 },
+ },
};
static const struct dis386 opc_ext_rm_table[][8] = {
{ "(bad)", { XX } },
{ "(bad)", { XX } },
},
+ {
+ /* OPC_EXT_RM_5 */
+ { "swapgs", { Skip_MODRM } },
+ { "rdtscp", { Skip_MODRM } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ },
};
#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
}
static void
-INVLPG_Fixup (int bytemode, int sizeflag)
-{
- const char *alt;
-
- switch (*codep)
- {
- case 0xf8:
- alt = "swapgs";
- break;
- case 0xf9:
- alt = "rdtscp";
- break;
- default:
- OP_M (bytemode, sizeflag);
- return;
- }
- /* Override "invlpg". */
- strcpy (obuf + strlen (obuf) - 6, alt);
- codep++;
-}
-
-static void
BadOp (void)
{
/* Throw away prefixes and 1st. opcode byte. */
projects / external / binutils.git / commitdiff