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[Arm64] stlr for JIT_WriteBarrier
authorSteve MacLean, Qualcomm Datacenter Technologies, Inc <sdmaclea@qti.qualcomm.com>
Fri, 26 May 2017 00:08:39 +0000 (00:08 +0000)
committerRuss Keldorph <russ.keldorph@microsoft.com>
Thu, 8 Jun 2017 15:54:37 +0000 (08:54 -0700)
Commit migrated from https://github.com/dotnet/coreclr/commit/057686e1789897e453100086209a72d9e3353073

src/coreclr/src/vm/arm64/asmhelpers.S patch | blob | history
src/coreclr/src/vm/arm64/asmhelpers.asm patch | blob | history

diff --git a/src/coreclr/src/vm/arm64/asmhelpers.S b/src/coreclr/src/vm/arm64/asmhelpers.S
index a3aec32..2e1d029 100644 (file)
--- a/src/coreclr/src/vm/arm64/asmhelpers.S
+++ b/src/coreclr/src/vm/arm64/asmhelpers.S
@@ -267,8 +267,7 @@ WRITE_BARRIER_END JIT_CheckedWriteBarrier
 //   x17  : trashed (ip1) if FEATURE_USE_SOFTWARE_WRITE_WATCH_FOR_GC_HEAP
 //
 WRITE_BARRIER_ENTRY JIT_WriteBarrier
-    dmb  ish
-    str  x15, [x14]
+    stlr  x15, [x14]
 
 #ifdef WRITE_BARRIER_CHECK
     // Update GC Shadow Heap
diff --git a/src/coreclr/src/vm/arm64/asmhelpers.asm b/src/coreclr/src/vm/arm64/asmhelpers.asm
index f303f82..8da2151 100644 (file)
--- a/src/coreclr/src/vm/arm64/asmhelpers.asm
+++ b/src/coreclr/src/vm/arm64/asmhelpers.asm
@@ -326,8 +326,7 @@ NotInHeap
 ;   x15  : trashed
 ;
     WRITE_BARRIER_ENTRY JIT_WriteBarrier
-        dmb      ish
-        str      x15, [x14]
+        stlr     x15, [x14]
 
 #ifdef WRITE_BARRIER_CHECK
         ; Update GC Shadow Heap  
Domain: Dotnet / Core;